Please use this identifier to cite or link to this item: http://hdl.handle.net/10553/46921
Title: Influence of gate geometry in integrated MOS varactors on accumulation mode for RF
Authors: Amselem, E.
González, B. 
García, J. 
Aldea, I.
Marrero Martín, Margarita Luisa 
Iturri, A. G.
Del Pino, J. 
Khemchandani, S. L. 
Hernández, A. 
UNESCO Clasification: 3307 Tecnología electrónica
Keywords: CMOS integrated circuits
MOS integrated circuits
radiofrequency integrated circuits
Varactors
Issue Date: 2007
Journal: 2007 Spanish Conference on Electron Devices, Proceedings
Conference: 6th Spanish Conference on Electron Devices 
Abstract: Driven by the many applications that varactors have in RF integrated blocks, this work analyzes the influence of gate geometry (width and length) on integrated accumulation MOS varactors. For this purpose, a number of varactors have been designed and fabricated on a 0.8 mu m CMOS standard technology. The most relevant parameters: quality factor, tuning range, and capacitance, are simulated and compared against measurements. Some design considerations are reported.
URI: http://hdl.handle.net/10553/46921
ISBN: 978-1-4244-0868-9
DOI: 10.1109/SCED.2007.383997
Source: 2007 Spanish Conference on Electron Devices, Proceedings (4271170), p. 68-71
Appears in Collections:Actas de congresos
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