Please use this identifier to cite or link to this item: http://hdl.handle.net/10553/46813
DC FieldValueLanguage
dc.contributor.authorMadroñal, D.-
dc.contributor.authorLazcano, R.-
dc.contributor.authorFabelo, H.-
dc.contributor.authorOrtega, S.-
dc.contributor.authorCallicó, G. M.-
dc.contributor.authorJuarez, E.-
dc.contributor.authorSanz, C.-
dc.date.accessioned2018-11-23T08:28:27Z-
dc.date.available2018-11-23T08:28:27Z-
dc.date.issued2017-
dc.identifier.isbn9791092279153-
dc.identifier.issn2164-9766-
dc.identifier.otherWoS-
dc.identifier.urihttp://hdl.handle.net/10553/46813-
dc.description.abstractIn this paper, a study of the parallel exploitation of a Support Vector Machine (SVM) classifier with a linear kernel running on a Massively Parallel Processor Array platform is exposed. This system joins 256 cores working in parallel and grouped in 16 different clusters. The main objective of the research has been to develop an optimal implementation of the SVM classifier on a MPPA platform whilst the architectural bottlenecks of the hyperspectral image classifier are analyzed. Experimenting with medical images, the parallelization of the SVM classification has been conducted using three strategies: i) single- and multi-core processing, ii) single- and multi-cluster analysis and iii) single- and double-buffer execution. As a result, an average core processing speedup of 11.8 has been achieved when parallelizing the SVM classification process in a single cluster. On the contrary, since data communication accounts for 34.7% of the total execution time in the sequential case, the total speedup is upper-bounded to 2.9. Using a double-buffer methodology, a total speedup of 2.84 has been achieved on a single cluster. At last, the feasibility of a portable version of a linear SVM has been demonstrated.-
dc.languageeng-
dc.relation.ispartofProceedings Of The 2016 Conference On Design And Architectures For Signal & Image Processing-
dc.sourceConference on Design and Architectures for Signal and Image Processing, DASIP[ISSN 2164-9766] (7853812), p. 154-160-
dc.subject3307 Tecnología electrónica-
dc.subject.otherHyperspectral imaging-
dc.subject.otherParallel processing-
dc.subject.otherSupport vector machine classification-
dc.subject.otherKernel-
dc.subject.otherMathematical model-
dc.titleHyperspectral image classification using a parallel implementation of the linear SVM on a Massively Parallel Processor Array (MPPA) platform-
dc.typeinfo:eu-repo/semantics/conferenceObject-
dc.typeConferenceObject-
dc.relation.conference2016 Conference on Design and Architectures for Signal and Image Processing, DASIP 2016-
dc.identifier.doi10.1109/DASIP.2016.7853812-
dc.identifier.scopus85014443158-
dc.identifier.isi000405720300019-
dc.contributor.authorscopusid57192829417-
dc.contributor.authorscopusid57192839213-
dc.contributor.authorscopusid56405568500-
dc.contributor.authorscopusid57189334144-
dc.contributor.authorscopusid56006321500-
dc.contributor.authorscopusid36447485600-
dc.contributor.authorscopusid7006751614-
dc.description.lastpage160-
dc.identifier.issue7853812-
dc.description.firstpage154-
dc.investigacionIngeniería y Arquitectura-
dc.type2Actas de congresos-
dc.contributor.daisngid3360488-
dc.contributor.daisngid3634522-
dc.contributor.daisngid2096372-
dc.contributor.daisngid1812298-
dc.contributor.daisngid506422-
dc.contributor.daisngid693458-
dc.contributor.daisngid384271-
dc.description.numberofpages7-
dc.identifier.eisbn979-1-0922-7915-3-
dc.utils.revision-
dc.contributor.wosstandardWOS:Madronal, D-
dc.contributor.wosstandardWOS:Lazcano, R-
dc.contributor.wosstandardWOS:Fabelo, H-
dc.contributor.wosstandardWOS:Ortega, S-
dc.contributor.wosstandardWOS:Callico, GM-
dc.contributor.wosstandardWOS:Juarez, E-
dc.contributor.wosstandardWOS:Sanz, C-
dc.date.coverdateJulio 2016-
dc.identifier.conferenceidevents121055-
dc.identifier.ulpgces
item.fulltextSin texto completo-
item.grantfulltextnone-
crisitem.event.eventsstartdate12-10-2016-
crisitem.event.eventsenddate14-10-2016-
crisitem.author.deptIUMA Sistemas de Información y Comunicaciones-
crisitem.author.deptIU de Microelectrónica Aplicada-
crisitem.author.deptDepartamento de Ingeniería Electrónica y Automática-
crisitem.author.orcid0000-0002-9794-490X-
crisitem.author.orcid0000-0002-7519-954X-
crisitem.author.orcid0000-0002-3784-5504-
crisitem.author.parentorgIU de Microelectrónica Aplicada-
crisitem.author.fullNameFabelo Gómez, Himar Antonio-
crisitem.author.fullNameOrtega Sarmiento, Samuel-
crisitem.author.fullNameMarrero Callicó, Gustavo Iván-
Appears in Collections:Actas de congresos
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