Identificador persistente para citar o vincular este elemento: http://hdl.handle.net/10553/46813
Título: Hyperspectral image classification using a parallel implementation of the linear SVM on a Massively Parallel Processor Array (MPPA) platform
Autores/as: Madroñal, D.
Lazcano, R.
Fabelo, H. 
Ortega, S. 
Callicó, G. M. 
Juarez, E.
Sanz, C.
Clasificación UNESCO: 3307 Tecnología electrónica
Palabras clave: Hyperspectral imaging
Parallel processing
Support vector machine classification
Kernel
Mathematical model
Fecha de publicación: 2017
Publicación seriada: Proceedings Of The 2016 Conference On Design And Architectures For Signal & Image Processing
Conferencia: 2016 Conference on Design and Architectures for Signal and Image Processing, DASIP 2016 
Resumen: In this paper, a study of the parallel exploitation of a Support Vector Machine (SVM) classifier with a linear kernel running on a Massively Parallel Processor Array platform is exposed. This system joins 256 cores working in parallel and grouped in 16 different clusters. The main objective of the research has been to develop an optimal implementation of the SVM classifier on a MPPA platform whilst the architectural bottlenecks of the hyperspectral image classifier are analyzed. Experimenting with medical images, the parallelization of the SVM classification has been conducted using three strategies: i) single- and multi-core processing, ii) single- and multi-cluster analysis and iii) single- and double-buffer execution. As a result, an average core processing speedup of 11.8 has been achieved when parallelizing the SVM classification process in a single cluster. On the contrary, since data communication accounts for 34.7% of the total execution time in the sequential case, the total speedup is upper-bounded to 2.9. Using a double-buffer methodology, a total speedup of 2.84 has been achieved on a single cluster. At last, the feasibility of a portable version of a linear SVM has been demonstrated.
URI: http://hdl.handle.net/10553/46813
ISBN: 9791092279153
ISSN: 2164-9766
DOI: 10.1109/DASIP.2016.7853812
Fuente: Conference on Design and Architectures for Signal and Image Processing, DASIP[ISSN 2164-9766] (7853812), p. 154-160
Colección:Actas de congresos
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