|Title:||Scalable video coding deblocking filter FPGA and ASIC implementation using high-level synthesis methodology||Authors:||Carballo, Pedro P.
Neris Tomé, Romén
Szydzik, Tomasz M.
|UNESCO Clasification:||3307 Tecnología electrónica||Keywords:||Field programmable gate arrays
Random access memory
|Issue Date:||2013||Journal:||Proceedings - 16th Euromicro Conference on Digital System Design, DSD 2013||Conference:||16th Euromicro Conference on Digital System Design (DSD)||Abstract:||This paper describes key concepts in the design and implementation of a deblocking filter (DF) for a H.264/SVC video decoder. The DF supports QCIF and CIF video formats with temporal and spatial scalability. The design flow starts from a SystemC functional model and has been refined using high-level synthesis methodology to RTL micro architecture. The process is guided with performance measurements (latency, cycle time, power, resource utilization) with the objective of assuring the quality of results of the final system. The functional model of the DF is created in an incremental way from the AVC DF model using OpenSVC source code as reference. The design flow continues with the logic synthesis and the implementation on the FPGA using various strategies. The FPGA implementation is capable to run at 100 MHz, and macro blocks are processed in 6, 500 clock cycles for a throughput of 130 fps for QCIF format and 37 fps for CIF format. A validation platform has been developed using the embedded PowerPC processor in the FPGA, composing a SoC that integrates the tasks for frame generation and visualization on a TFT screen. The FPGA implements both the DF core and a General Purpose Memory Controller (GPMC) slave core. Both cores are connected to the PowerPC440 embedded processor using Local Link interfaces. The FPGA also contains a local memory capable of storing information necessary to filter a complete frame and to store a decoded picture frame. The complete system is implemented in a Virtex5 FX70T device. An ASIC implementation of the deblocking filter has been done using UMC CMOS 65nm technology. The ASIC implementation is running at 181.8 MHz, occupying an area of 596, 392.4 μm 2 .||URI:||http://hdl.handle.net/10553/45646||ISBN:||9780769550749||DOI:||10.1109/DSD.2013.52||Source:||Proceedings - 16th Euromicro Conference on Digital System Design, DSD 2013 (6628307), p. 415-422|
|Appears in Collections:||Actas de congresos|
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