Integer and control units for a GaAs 32-bit RISC processor

Abstract

In this paper we present the design and simulation of the Integer and Control Units of AsGaR, a RISC processor featuring a proprietary streamlined architecture. Running at a clock speed of 440 MHz, it delivers a peak throughput of 110 MIPS. The work reported here makes clear the level of complexity faced by this kind of designs and the need to use a wholistic approach considering all aspects of system implementation. AsGaR has been implemented in a TriQuint GaAs process, using a standard cell library. The current shortage of tools for GaAs design has been overcome by adapting the Cadence/Edge environment to this technology. Simulation has been done by describing the cell library in System Hilo and Verilog.