Implementation of CORDIC processor for CFFT computation in gallium arsenide technology

Abstract

In this paper the architecture and the implementation of a complex fast Fourier transform (CFFT) processor using 0.8 /spl mu/m gallium arsenide technology is presented. The processor is based upon the CORDIC algorithm in which elementary functions use only add and shift operations instead of the more conventional multiply and add hardware. In this architecture functional primitives were designed and extensively simulated taking into account process variations and in particular up to /spl plusmn/3/spl sigma/ of threshold voltage variation. Issues pertaining to the design of a 1024 point CFFT processor with 16 bit data and operating up to 1 GHz are discussed.