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Please use this identifier to cite or link to this item: http://hdl.handle.net/10553/45094
DC FieldValueLanguage
dc.contributor.authorLópez Feliciano, José Franciscoen_US
dc.contributor.authorEshraghian, K.en_US
dc.contributor.authorMcGeever, M. K.en_US
dc.contributor.authorNunez, A.en_US
dc.contributor.authorSarmiento, R.en_US
dc.date.accessioned2018-11-22T07:13:20Z-
dc.date.available2018-11-22T07:13:20Z-
dc.date.issued1995en_US
dc.identifier.urihttp://hdl.handle.net/10553/45094-
dc.description.abstractGallium arsenide (GaAs) technology, because of its high speed, offers an alternative to silicon (Si). For the particular case of digital memories, speed has great importance taking into account that the success of a high-performance microprocessor depends greatly on how fast data are obtained and sent to memory. However, GaAs presents some problems when implementing memories, mainly due to its leaky characteristics and the small output logic swing compared to that produced in MOS devices. In this paper, novel architectures are proposed in order to overcome these problems. As a result, different designs have been implemented for 2- and 5-kbit ROMs, and for a 14-kbit DRAM.en_US
dc.languageengen_US
dc.relation.ispartofRecords of the IEEE International Workshop on Memory Technology, Design and Testingen_US
dc.sourceRecords of the IEEE International Workshop on Memory Technology, Design and Testing, p. 103-108en_US
dc.subject3307 Tecnología electrónicaen_US
dc.subject.otherGallium arsenideen_US
dc.subject.otherMESFETsen_US
dc.subject.otherLeakage currenten_US
dc.subject.otherVery large scale integrationen_US
dc.subject.otherFETsen_US
dc.titleGallium arsenide MESFET memory architecturesen_US
dc.typeinfo:eu-repo/semantics/conferenceObjecten_US
dc.typeConferenceObjecten_US
dc.relation.conferenceRecords of the 1995 IEEE International Workshop on Memory Technology, Design and Testingen_US
dc.identifier.scopus0029204076-
dc.contributor.authorscopusid7404444793-
dc.contributor.authorscopusid7007041524-
dc.contributor.authorscopusid6505820260-
dc.contributor.authorscopusid7103279517-
dc.contributor.authorscopusid35609452100-
dc.description.lastpage108en_US
dc.description.firstpage103en_US
dc.investigacionIngeniería y Arquitecturaen_US
dc.type2Actas de congresosen_US
dc.utils.revisionSíen_US
dc.date.coverdateEnero 1995en_US
dc.identifier.conferenceidevents121243-
dc.identifier.ulpgcSíes
dc.contributor.buulpgcBU-INGen_US
item.grantfulltextnone-
item.fulltextSin texto completo-
crisitem.event.eventsstartdate07-08-1995-
crisitem.event.eventsenddate08-08-1995-
crisitem.author.deptGIR IUMA: Diseño de Sistemas Electrónicos Integrados para el procesamiento de datos-
crisitem.author.deptIU de Microelectrónica Aplicada-
crisitem.author.deptDepartamento de Ingeniería Electrónica y Automática-
crisitem.author.deptGIR IUMA: Sistemas de Información y Comunicaciones-
crisitem.author.deptIU de Microelectrónica Aplicada-
crisitem.author.deptDepartamento de Ingeniería Electrónica y Automática-
crisitem.author.deptGIR IUMA: Diseño de Sistemas Electrónicos Integrados para el procesamiento de datos-
crisitem.author.deptIU de Microelectrónica Aplicada-
crisitem.author.deptDepartamento de Ingeniería Electrónica y Automática-
crisitem.author.orcid0000-0002-6304-2801-
crisitem.author.orcid0000-0003-1295-1594-
crisitem.author.orcid0000-0002-4843-0507-
crisitem.author.parentorgIU de Microelectrónica Aplicada-
crisitem.author.parentorgIU de Microelectrónica Aplicada-
crisitem.author.parentorgIU de Microelectrónica Aplicada-
crisitem.author.fullNameLópez Feliciano, José Francisco-
crisitem.author.fullNameNúñez Ordóñez, Antonio-
crisitem.author.fullNameSarmiento Rodríguez, Roberto-
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