Identificador persistente para citar o vincular este elemento:
http://hdl.handle.net/10553/45093
| Título: | High performance GaAs pseudo dynamic class of logic | Autores/as: | López Feliciano, José Francisco Sarmiento, R. Nunez, A. Eshraghian, K. |
Clasificación UNESCO: | 3307 Tecnología electrónica | Palabras clave: | Gallium arsenide Power dissipation CMOS technology Leakage current High performance computing, et al. |
Fecha de publicación: | 1996 | Editor/a: | 1063-0988 | Publicación seriada: | Proceedings of the Annual IEEE International ASIC Conference and Exhibit | Conferencia: | 9th Annual IEEE International ASIC Conference and Exhibit | Resumen: | In this paper Pseudo Dynamic Latched Logic (PDLL) is introduced. This class of logic takes benefits of both static and dynamic structures, by using a permanently refreshing circuitry which allows functionality even at low frequencies and high temperatures. Moreover, because of its dynamic structure, complex gates are possible with a subsequent delay-area-power reduction. PDLL performance is demonstrated by implementing a 4-bit carry lookahead adder fully operative in a range of 6 to 100/spl deg/C. The adder operates at 0.8 GHz with an associated power dissipation of only 5.2 mW. | URI: | http://hdl.handle.net/10553/45093 | ISBN: | 0-7803-3302-0 | ISSN: | 1063-0988 | Fuente: | Proceedings of the Annual IEEE International ASIC Conference and Exhibit[ISSN 1063-0988], p. 51-55 |
| Colección: | Actas de congresos |
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