Please use this identifier to cite or link to this item: http://hdl.handle.net/10553/45093
Title: High performance GaAs pseudo dynamic class of logic
Authors: Lopez, J. F. 
Sarmiento, R. 
Nunez, A. 
Eshraghian, K.
UNESCO Clasification: 3307 Tecnología electrónica
Keywords: Gallium arsenide
Power dissipation
CMOS technology
Leakage current
High performance computing
Frequency
Logic devices
Issue Date: 1996
Publisher: 1063-0988
Journal: Proceedings of the Annual IEEE International ASIC Conference and Exhibit
Conference: 9th Annual IEEE International ASIC Conference and Exhibit 
Proceedings of the 1996 9th Annual IEEE International ASIC Conference and Exhibit 
Abstract: In this paper Pseudo Dynamic Latched Logic (PDLL) is introduced. This class of logic takes benefits of both static and dynamic structures, by using a permanently refreshing circuitry which allows functionality even at low frequencies and high temperatures. Moreover, because of its dynamic structure, complex gates are possible with a subsequent delay-area-power reduction. PDLL performance is demonstrated by implementing a 4-bit carry lookahead adder fully operative in a range of 6 to 100/spl deg/C. The adder operates at 0.8 GHz with an associated power dissipation of only 5.2 mW.
URI: http://hdl.handle.net/10553/45093
ISBN: 0-7803-3302-0
ISSN: 1063-0988
Source: Proceedings of the Annual IEEE International ASIC Conference and Exhibit[ISSN 1063-0988], p. 51-55
Appears in Collections:Actas de congresos
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