High performance GaAs pseudo dynamic class of logic

Abstract

In this paper Pseudo Dynamic Latched Logic (PDLL) is introduced. This class of logic takes benefits of both static and dynamic structures, by using a permanently refreshing circuitry which allows functionality even at low frequencies and high temperatures. Moreover, because of its dynamic structure, complex gates are possible with a subsequent delay-area-power reduction. PDLL performance is demonstrated by implementing a 4-bit carry lookahead adder fully operative in a range of 6 to 100/spl deg/C. The adder operates at 0.8 GHz with an associated power dissipation of only 5.2 mW.