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Title: | Gallium arsenide pseudo-dynamic latched logic | Authors: | López Feliciano, José Eshraghian, K. Sarmiento, R. Núñez, A. |
UNESCO Clasification: | 3307 Tecnología electrónica | Keywords: | Gallium compounds Pipeline processing Integrated circuit design Integrated circuit noise FET logic devices |
Issue Date: | 1996 | Publisher: | 0013-5194 | Journal: | Electronics letters | Abstract: | A new GaAs logic family, pseudo-dynamic latched logic (PDLL). is introduced. Compared with traditional static GaAs logic families, PDLL allows complex gate design with less power dissipation. In addition, it overcomes problems associated with charge degradation in the storage nodes in dynamic logic gates, and operates at relatively high temperatures. PDLL is self-latched which leads to the possibility of implementing compact pipeline systems. | URI: | http://hdl.handle.net/10553/45092 | ISSN: | 0013-5194 | DOI: | 10.1049/el:19960926 | Source: | Electronics Letters[ISSN 0013-5194],v. 32, p. 1353-1354 |
Appears in Collections: | Artículos |
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