Please use this identifier to cite or link to this item: http://hdl.handle.net/10553/45065
Title: High-performance VLSI architecture for video processing
Authors: Navarro, Héctor
Montiel-Nelson, Juan A. 
Sosa, Javier 
García, José C.
Sarmiento, R. 
Nooshabadi, Saeid
UNESCO Clasification: 3307 Tecnología electrónica
Keywords: Arithmetic coding
VLSI
M-ABRC
VSW
Issue Date: 2003
Journal: Proceedings of SPIE - The International Society for Optical Engineering 
Conference: Conference on VLSI Circuits and Systems 
VLSI Circuits and Systems 
Abstract: Arithmetic coding is the data compression techniques, which encodes the data by generating the code string that represents a functional value between 0 and 1. In this paper, we propose a modified-Adaptive Binary-RC (Range Coder) or M-ABRC. Our algorithm minimizes the multiplication bit capacity through introducing the VLSI architecture, proposed algorithm uses the LUP (Look UP Table)-VSW (Virtual Sliding Window) for the probability estimation. In order to achieve the higher compression rate, our method M-ABRC has been implemented, this in terms provides the better adoption probability in encoding phase and also gives the absolute estimation of low-EBS(entropy binary sources). Moreover In order to evaluate the algorithm we have compared with the several existing technique, comparison takes place based on the two parameter i.e. device utilization and the power dissipation (static and dynamic).
URI: http://hdl.handle.net/10553/45065
ISBN: 0-8194-4977-6
ISSN: 0277-786X
DOI: 10.1117/12.498585
Source: Proceedings of SPIE - The International Society for Optical Engineering[ISSN 0277-786X],v. 5117, p. 175-186
Appears in Collections:Actas de congresos
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