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Title: High-speed clock recovery unit based on a phase aligner
Authors: Tejera, E.
Esper-Chain, R. 
Tobajas, F. 
De Armas Sosa, Valentín 
Sarmiento, R. 
UNESCO Clasification: 3307 Tecnología electrónica
Keywords: Clock and data recovery circuits (CDR circuits)
Phase interpolator
Issue Date: 2003
Journal: Proceedings of SPIE - The International Society for Optical Engineering 
Conference: Conference on VLSI Circuits and Systems 
VLSI Circuits and Systems 
Abstract: Nowadays clock recovery units (CRU) are key elements in high speed digital communication systems. For an efficient operation, these units should generate a low jitter clock based on the NRZ received data, and be tolerant to long absence of transitions. Architectures based on Hogge phase detectors have been widely used, nevertheless, they are very sensitive to jitter of the received data and they have a limited tolerance to the absence of transitions. This paper shows a novel high speed clock recovery unit based on a phase aligner. The system allows a very fast clock recovery with a low jitter, moreover, it is very resistant to absence of transitions. The design is based on eight phases obtained from a reference incoherent clock running at the nominal frequency of the received signal. The phase alignment system chooses, as starting point, the two phases closest to the data phase. This allows a maximum error of 45° between the clock and data signal phases. Furthermore, the system includes a feed-back loop that interpolates the chosen phases to reduce the phase error to zero. Due to the high stability and reduced tolerance of the local reference clock, the jitter obtained is highly reduced and the system becomes able to operate under long absence of transitions. These performances make this design suitable for systems such as high speed serial link technologies.
ISSN: 0277-786X
DOI: 10.1117/12.498653
Source: Proceedings of SPIE - The International Society for Optical Engineering[ISSN 0277-786X],v. 5117, p. 106-115
Appears in Collections:Actas de congresos
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