Please use this identifier to cite or link to this item: http://hdl.handle.net/10553/45063
DC FieldValueLanguage
dc.contributor.authorTejera, E.en_US
dc.contributor.authorEsper-Chain, R.en_US
dc.contributor.authorTobajas, F.en_US
dc.contributor.authorDe Armas Sosa, Valentínen_US
dc.contributor.authorSarmiento, R.en_US
dc.date.accessioned2018-11-22T06:59:13Z-
dc.date.available2018-11-22T06:59:13Z-
dc.date.issued2003en_US
dc.identifier.issn0277-786Xen_US
dc.identifier.urihttp://hdl.handle.net/10553/45063-
dc.description.abstractNowadays clock recovery units (CRU) are key elements in high speed digital communication systems. For an efficient operation, these units should generate a low jitter clock based on the NRZ received data, and be tolerant to long absence of transitions. Architectures based on Hogge phase detectors have been widely used, nevertheless, they are very sensitive to jitter of the received data and they have a limited tolerance to the absence of transitions. This paper shows a novel high speed clock recovery unit based on a phase aligner. The system allows a very fast clock recovery with a low jitter, moreover, it is very resistant to absence of transitions. The design is based on eight phases obtained from a reference incoherent clock running at the nominal frequency of the received signal. The phase alignment system chooses, as starting point, the two phases closest to the data phase. This allows a maximum error of 45° between the clock and data signal phases. Furthermore, the system includes a feed-back loop that interpolates the chosen phases to reduce the phase error to zero. Due to the high stability and reduced tolerance of the local reference clock, the jitter obtained is highly reduced and the system becomes able to operate under long absence of transitions. These performances make this design suitable for systems such as high speed serial link technologies.en_US
dc.languageengen_US
dc.relation.ispartofProceedings of SPIE - The International Society for Optical Engineeringen_US
dc.sourceProceedings of SPIE - The International Society for Optical Engineering[ISSN 0277-786X],v. 5117, p. 106-115en_US
dc.subject3307 Tecnología electrónicaen_US
dc.subject.otherClock and data recovery circuits (CDR circuits)en_US
dc.subject.otherPhase interpolatoren_US
dc.subject.otherClocksen_US
dc.titleHigh-speed clock recovery unit based on a phase aligneren_US
dc.typeinfo:eu-repo/semantics/conferenceObjectes
dc.typeConferenceObjectes
dc.relation.conferenceConference on VLSI Circuits and Systems
dc.relation.conferenceVLSI Circuits and Systems
dc.identifier.doi10.1117/12.498653
dc.identifier.scopus0042329219-
dc.identifier.isi000183950600011
dc.contributor.authorscopusid6603254209-
dc.contributor.authorscopusid6602504574-
dc.contributor.authorscopusid6602389338-
dc.contributor.authorscopusid6603181073-
dc.contributor.authorscopusid35609452100-
dc.description.lastpage115-
dc.description.firstpage106-
dc.relation.volume5117-
dc.investigacionIngeniería y Arquitecturaen_US
dc.type2Actas de congresosen_US
dc.contributor.daisngid939534
dc.contributor.daisngid1984698
dc.contributor.daisngid26063230
dc.contributor.daisngid1262195
dc.contributor.daisngid116294
dc.utils.revisionen_US
dc.contributor.wosstandardWOS:Tejera, E
dc.contributor.wosstandardWOS:Esper-Chain, R
dc.contributor.wosstandardWOS:Tobajas, F
dc.contributor.wosstandardWOS:De Armas, V
dc.contributor.wosstandardWOS:Sarmiento, R
dc.date.coverdateSeptiembre 2003
dc.identifier.conferenceidevents120355
dc.identifier.ulpgces
item.fulltextSin texto completo-
item.grantfulltextnone-
crisitem.event.eventsstartdate19-05-2003-
crisitem.event.eventsstartdate19-05-2003-
crisitem.event.eventsenddate21-05-2003-
crisitem.event.eventsenddate21-05-2003-
crisitem.author.deptGIR IUMA: Equipos y Sistemas de Comunicación-
crisitem.author.deptIU de Microelectrónica Aplicada-
crisitem.author.deptDepartamento de Ingeniería Electrónica y Automática-
crisitem.author.deptGIR IUMA: Sistemas de Información y Comunicaciones-
crisitem.author.deptIU de Microelectrónica Aplicada-
crisitem.author.deptDepartamento de Ingeniería Electrónica y Automática-
crisitem.author.deptGIR IUMA: Sistemas de Información y Comunicaciones-
crisitem.author.deptIU de Microelectrónica Aplicada-
crisitem.author.deptDepartamento de Ingeniería Electrónica y Automática-
crisitem.author.deptGIR IUMA: Diseño de Sistemas Electrónicos Integrados para el procesamiento de datos-
crisitem.author.deptIU de Microelectrónica Aplicada-
crisitem.author.deptDepartamento de Ingeniería Electrónica y Automática-
crisitem.author.orcid0000-0002-8381-969X-
crisitem.author.orcid0000-0002-3379-5052-
crisitem.author.orcid0000-0002-1017-8107-
crisitem.author.orcid0000-0002-4843-0507-
crisitem.author.parentorgIU de Microelectrónica Aplicada-
crisitem.author.parentorgIU de Microelectrónica Aplicada-
crisitem.author.parentorgIU de Microelectrónica Aplicada-
crisitem.author.parentorgIU de Microelectrónica Aplicada-
crisitem.author.fullNameEsper-Chaín Falcón, Roberto-
crisitem.author.fullNameTobajas Guerrero, Félix Bernardo-
crisitem.author.fullNameDe Armas Sosa, Valentín-
crisitem.author.fullNameSarmiento Rodríguez, Roberto-
Appears in Collections:Actas de congresos
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