|Title:||System-level verification methodology for advanced switch fabrics||Authors:||Sosa, J.
Montiel-Nelson, Juan A.
|UNESCO Clasification:||3307 Tecnología electrónica||Keywords:||Verification
|Issue Date:||2003||Journal:||Proceedings of SPIE - The International Society for Optical Engineering||Conference:||Conference on VLSI Circuits and Systems
VLSI Circuits and Systems
|Abstract:||A system-level verification methodology for advanced switch fabrics is introduced in this paper. Due to the short life cycles and the changing standards, the design and verification of new products require new design and verification tools. As result of our methodology, a verification framework is also presented. The decomposition of each interface of the switch fabric allows the reconfiguration of the framework, when a new revision of the design is defined. This idea promotes the reuse of the main interface code and verification statements. The development of the verification framework in C++, 'e'1 and Verilog demonstrates that our methodology can be applied independently of the programming language. New features, added to the framework, such as error insertion, enhance the verification coverage for corner cases. On the other hand, the golden reference layer is the key of the automatic verification, because a high level model can be used as reference model to check the correctness of the design automatically. Several commercial and non-commercial advanced switch fabrics have been verified using this method. The usefulness of the proposed methodology is demonstrated by GigaStream Chip Set2 functional success and the saving of a 60% in the verification time per effort unit.||URI:||http://hdl.handle.net/10553/45060||ISBN:||0-8194-4977-6||ISSN:||0277-786X||DOI:||10.1117/12.498612||Source:||Proceedings of SPIE - The International Society for Optical Engineering[ISSN 0277-786X],v. 5117, p. 187-198|
|Appears in Collections:||Actas de congresos|
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