Please use this identifier to cite or link to this item: http://hdl.handle.net/10553/45054
Title: Efficient method to obtain the entire active area against circuit delay time trade-off curve in gate sizing
Authors: Montiel-Nelson, J. A. 
Sosa, J. 
Navarro, H.
Sarmiento, R. 
Núñez, A. 
UNESCO Clasification: 3307 Tecnología electrónica
Keywords: Circuit optimisation
Combinational circuits
Logic gates
Delay
Integrated logic circuits
linear programming
Multivalued logic circuits
Issue Date: 2005
Journal: IEE Proceedings: Circuits, Devices and Systems 
Abstract: The authors are concerned with the optimisation of combinational logic circuits. The competing factors, active area and delay time, are considered in the optimisation. The total active area is assumed to be a linear function of the gate sizes. There is a critical path whose delay time, the longest delay time of the circuit, depends on the sizes of the individual gates. This path will change many times during the optimisation. The optimisation process is used to produce the tradeoff curve. The proposed methodology is based on the optimisation of the circuit critical path. This is a gate sizing problem on those paths that define the delay time of a circuit. Given a drive size for all the gates of the circuit, the trade-off curve contains design space points of minimum delay time and active area. A variable-sized subset of the Boolean network is optimised. Only the gates in the circuit critical path are optimised. The gates in the Boolean network which are not in the critical path do not need to be optimised. An efficient method is proposed for updating the critical path as the trade-off curve is obtained. Performance comparison and results were obtained over the set of MCNC two-level and combinational multilevel benchmark circuits. The proposed methodology produces trade-off curves, in relatively large circuits, with a great reduction in number of variables and run-time compared with the original full problem. In the proposed method, the number of variables is reduced by a factor of up to 7.3 times relative to the original full problem. The run-time behaviour is excellent, with an improvement between 1.5 and 32.5 times less CPU time compared with computation of the full Boolean network. With a higher gate count of the circuit, there are greater improvements in both run-time and number of variables.
URI: http://hdl.handle.net/10553/45054
ISSN: 1350-2409
DOI: 10.1049/ip-cds:20040779
Source: IEE Proceedings: Circuits, Devices and Systems[ISSN 1350-2409],v. 152, p. 133-145
Appears in Collections:Actas de congresos
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