A low power 2.5 Gbps 1:32 deserializer in SiGe BiCMOS technology

Abstract

In this paper, the implementation of a 2.5 Gbps 1:32 deserializer in SiGe BiCMOS technology using standard cells and ECL bipolar circuits in order to minimize power consumption, is presented. The deserializer is composed of two main circuits: a demultiplexer and a clock distribution network. The architecture of the demultiplexer is based on a tree structure which allows using CMOS technology for low-speed stages. Clock signals are generated by the clock distribution network which is formed by static frequency dividers. In order to adapt both logic families, an ECL to CMOS converter was designed. High-speed ECL circuits were implemented full-custom with Cadence Virtuoso whereas standard cells were used for CMOS circuits were designed with Silicon Ensemble. Functionality has been verified through post-layout simulations performed in all technology's corner cases. The final IC has an area of 700 mum times 1045 mum and a total power consumption of 300 mW approximation.