Please use this identifier to cite or link to this item:
Title: A low power 2.5 Gbps 1:32 deserializer in SiGe BiCMOS technology
Authors: Tobajas, Félix B. 
Esper-Chaín, Roberto 
Regidor, R.
Santana, O. 
Sarmiento Rodríguez, Roberto 
UNESCO Clasification: 3307 Tecnología electrónica
Keywords: Germanium silicon alloys
Silicon germanium
BiCMOS integrated circuits
CMOS technology
Energy consumption, et al
Issue Date: 2006
Publisher: Institute of Electrical and Electronics Engineers (IEEE) 
Conference: 9th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems 
Abstract: In this paper, the implementation of a 2.5 Gbps 1:32 deserializer in SiGe BiCMOS technology using standard cells and ECL bipolar circuits in order to minimize power consumption, is presented. The deserializer is composed of two main circuits: a demultiplexer and a clock distribution network. The architecture of the demultiplexer is based on a tree structure which allows using CMOS technology for low-speed stages. Clock signals are generated by the clock distribution network which is formed by static frequency dividers. In order to adapt both logic families, an ECL to CMOS converter was designed. High-speed ECL circuits were implemented full-custom with Cadence Virtuoso whereas standard cells were used for CMOS circuits were designed with Silicon Ensemble. Functionality has been verified through post-layout simulations performed in all technology's corner cases. The final IC has an area of 700 mum times 1045 mum and a total power consumption of 300 mW approximation.
ISBN: 1-4244-0184-2
DOI: 10.1109/DDECS.2006.1649564
Source: 2006 IEEE Design and Diagnostics of Electronic Circuits and systems,v. 2006 (1649564), p. 19-24
Appears in Collections:Actas de congresos
Show full item record


checked on Apr 14, 2024

Page view(s)

checked on Feb 10, 2024

Google ScholarTM




Export metadata

Items in accedaCRIS are protected by copyright, with all rights reserved, unless otherwise indicated.