Identificador persistente para citar o vincular este elemento: http://hdl.handle.net/10553/45040
Título: Towards the implementation of a baseline H.264/AVC decoder onto a reconfigurable architecture
Autores/as: López, S. 
Kanstein, A.
López Feliciano, José Francisco 
Berekovic, M.
Sarmiento, R. 
Mignolet, J. Y.
Clasificación UNESCO: 3307 Tecnología electrónica
Palabras clave: Image coding
Video signal processing
Motion estimation
Fecha de publicación: 2007
Publicación seriada: Proceedings of SPIE - The International Society for Optical Engineering 
Conferencia: Conference on VLSI Circuits and Systems III 
Resumen: The decoding of a H.264/AVC bitstream represents a complex and time-consuming task. Due to this reason, efficient implementations in terms of performance and flexibility are mandatory for real time applications. In this sense, the mapping of the motion compensation and deblocking filtering stages onto a coarse-grained reconfigurable architecture named ADRES (Architecture for Dynamically Reconfigurable Embedded Systems) is presented in this paper. The results obtained show a considerable reduction in the number of cycles and memory accesses needed to perform the motion compensation as well as an increase in the degree of parallelism when compared with an implementation on a Very Long Instruction Word (VLIW) dedicated processor.
URI: http://hdl.handle.net/10553/45040
ISBN: 978-0-8194-6718-8
ISSN: 0277-786X
DOI: 10.1117/12.722042
Fuente: Proceedings of SPIE - The International Society for Optical Engineering[ISSN 0277-786X],v. 6590 (65900A)
Colección:Actas de congresos
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