Please use this identifier to cite or link to this item:
Title: Towards the implementation of a baseline H.264/AVC decoder onto a reconfigurable architecture
Authors: López, S. 
Kanstein, A.
López Feliciano, José Francisco 
Berekovic, M.
Sarmiento, R. 
Mignolet, J. Y.
UNESCO Clasification: 3307 Tecnología electrónica
Keywords: Image coding
Video signal processing
Motion estimation
Issue Date: 2007
Journal: Proceedings of SPIE - The International Society for Optical Engineering 
Conference: Conference on VLSI Circuits and Systems III 
Abstract: The decoding of a H.264/AVC bitstream represents a complex and time-consuming task. Due to this reason, efficient implementations in terms of performance and flexibility are mandatory for real time applications. In this sense, the mapping of the motion compensation and deblocking filtering stages onto a coarse-grained reconfigurable architecture named ADRES (Architecture for Dynamically Reconfigurable Embedded Systems) is presented in this paper. The results obtained show a considerable reduction in the number of cycles and memory accesses needed to perform the motion compensation as well as an increase in the degree of parallelism when compared with an implementation on a Very Long Instruction Word (VLIW) dedicated processor.
ISBN: 978-0-8194-6718-8
ISSN: 0277-786X
DOI: 10.1117/12.722042
Source: Proceedings of SPIE - The International Society for Optical Engineering[ISSN 0277-786X],v. 6590 (65900A)
Appears in Collections:Actas de congresos
Show full item record

Google ScholarTM




Export metadata

Items in accedaCRIS are protected by copyright, with all rights reserved, unless otherwise indicated.