|Title:||An efficient double-filter hardware architecture for H.264/AVC deblocking filtering||Authors:||Tobajas, Félix
Callicó, Gustavo M.
Pérez, Pedro A.
De Armas Sosa, Valentín
|UNESCO Clasification:||3307 Tecnología electrónica||Keywords:||Automatic voltage control
Adaptive filters, et al
|Issue Date:||2008||Publisher:||0098-3063||Journal:||IEEE Transactions on Consumer Electronics||Abstract:||In this paper, a novel hardware architecture for real-time implementation of the adaptive deblocking filtering process specified by the H.264/AVC video coding standard, is presented. The deblocking filter is a computationally and data intensive tool resulting in an increased execution time of both the encoding and decoding processes. The proposed architecture is based on a double- filter strategy that results in a significant saving in filtering cycles, memory requirements and gate count when compared with state-of-the-art approaches. The proposed architecture is implemented in synthesizable HDL at RTL level and verified with the reference software. This hardware is designed to be used as part of a complete H.264/A VC video coding system.||URI:||http://hdl.handle.net/10553/45037||ISSN:||0098-3063||DOI:||10.1109/TCE.2008.4470035||Source:||IEEE Transactions on Consumer Electronics[ISSN 0098-3063],v. 54, p. 131-139|
|Appears in Collections:||Artículos|
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