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Title: Efficient lossy compression implementations of hyperspectral images: Tools, hardware platforms, and comparisons
Authors: García, Aday
Santos, Lucana 
López, Sebastián 
Callicó, Gustavo M. 
López, José Fco 
Sarmiento, Roberto 
UNESCO Clasification: 3307 Tecnología electrónica
Keywords: Image compression
Image coding
SPIHT algorithm
Issue Date: 2014
Publisher: 0277-786X
Journal: Proceedings of SPIE - The International Society for Optical Engineering 
Conference: Conference on Satellite Data Compression, Communications, and Processing X 
Abstract: Efficient onboard satellite hyperspectral image compression represents a necessity and a challenge for current and future space missions. Therefore, it is mandatory to provide hardware implementations for this type of algorithms in order to achieve the constraints required for onboard compression. In this work, we implement the Lossy Compression for Exomars (LCE) algorithm on an FPGA by means of high-level synthesis (HSL) in order to shorten the design cycle. Specifically, we use CatapultC HLS tool to obtain a VHDL description of the LCE algorithm from C-language specifications. Two different approaches are followed for HLS: on one hand, introducing the whole C-language description in CatapultC and on the other hand, splitting the C-language description in functional modules to be implemented independently with CatapultC, connecting and controlling them by an RTL description code without HLS. In both cases the goal is to obtain an FPGA implementation. We explain the several changes applied to the original Clanguage source code in order to optimize the results obtained by CatapultC for both approaches. Experimental results show low area occupancy of less than 15% for a SRAM-based Virtex-5 FPGA and a maximum frequency above 80 MHz. Additionally, the LCE compressor was implemented into an RTAX2000S antifuse-based FPGA, showing an area occupancy of 75% and a frequency around 53 MHz. All these serve to demonstrate that the LCE algorithm can be efficiently executed on an FPGA onboard a satellite. A comparison between both implementation approaches is also provided. The performance of the algorithm is finally compared with implementations on other technologies, specifically a graphics processing unit (GPU) and a single-threaded CPU
ISBN: 9781628410617
ISSN: 0277-786X
DOI: 10.1117/12.2051132
Source: Proceedings of SPIE - The International Society for Optical Engineering[ISSN 0277-786X],v. 9124 (912408)
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