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Title: A novel scalable Deblocking Filter architecture for H.264/AVC and SVC video codecs
Authors: Cervero, T. 
Otero, A.
López, S. 
De La Torre, E.
Callicó, G. 
Sarmiento, R. 
Riesgo, T.
UNESCO Clasification: 3307 Tecnología electrónica
Keywords: Filtering , Arrays , Proposals , Static VAr compensators , Parallel processing , Integrated circuits , H.264/AVC , SVC , deblocking-filter , FPGA , parallelism , scalability
Issue Date: 2011
Publisher: 1945-7871
Journal: Proceedings - IEEE International Conference on Multimedia and Expo
Conference: IEEE International Conference on Multimedia and Expo (ICME) 
2011 12th IEEE International Conference on Multimedia and Expo, ICME 2011 
Abstract: A highly parallel and scalable Deblocking Filter (DF) hardware architecture for H.264/AVC and SVC video codecs is presented in this paper. The proposed architecture mainly consists on a coarse grain systolic array obtained by replicating a unique and homogeneous Functional Unit (FU), in which a whole Deblocking-Filter unit is implemented. The proposal is also based on a novel macroblock-level parallelization strategy of the filtering algorithm which improves the final performance by exploiting specific data dependences. This way communication overhead is reduced and a more intensive parallelism in comparison with the existing state-of-the-art solutions is obtained. Furthermore, the architecture is completely flexible, since the level of parallelism can be changed, according to the application requirements. The design has been implemented in a Virtex-5 FPGA, and it allows filtering 4CIF (704 × 576 pixels @30 fps) video sequences in real-time at frequencies lower than 10.16 Mhz.
ISBN: 9781612843490
ISSN: 1945-7871
DOI: 10.1109/ICME.2011.6012075
Source: Proceedings - IEEE International Conference on Multimedia and Expo[ISSN 1945-7871] (6012075)
Appears in Collections:Actas de congresos
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