|Title:||Run-time scalable architecture for deblocking filtering in H.264/AVC-SVC video codecs||Authors:||Otero, A.
De La Torre, E.
|UNESCO Clasification:||3307 Tecnología electrónica||Keywords:||Filtering , Scalability , Arrays , Parallel processing , Static VAr compensators , Field programmable gate arrays , Reconfigurable architectures , scalable architecture , Deblocking Filter , H.264/AVC , SVC||Issue Date:||2011||Journal:||Proceedings - 21st International Conference on Field Programmable Logic and Applications, FPL 2011||Conference:||21st International Conference on Field Programmable Logic and Applications, FPL 2011||Abstract:||Systems relying on fixed hardware components with a static level of parallelism can suffer from an under use of logical resources, since they have to be designed for the worst-case scenario. This problem is especially important in video applications due to the emergence of new flexible standards, like Scalable Video Coding (SVC), which offer several levels of scalability. In this paper, Dynamic and Partial Reconfiguration (DPR) of modern FPGAs is used to achieve run-time variable parallelism, by using scalable architectures where the size can be adapted at run-time. Based on this proposal, a scalable Deblocking Filter core (DF), compliant with the H.264/AVC and SVC standards has been designed. This scalable DF allows run-time addition or removal of computational units working in parallel. Scalability is offered together with a scalable parallelization strategy at the macro block (MB) level, such that when the size of the architecture changes, MB filtering order is modified accordingly.||URI:||http://hdl.handle.net/10553/44407||ISBN:||9780769545295||DOI:||10.1109/FPL.2011.72||Source:||Proceedings - 21st International Conference on Field Programmable Logic and Applications, FPL 2011 (6044845), p. 369-375|
|Appears in Collections:||Actas de congresos|
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