|Title:||A hierarchical scheduling and management solution for dynamic reconfiguration in FPGA-based embedded systems||Authors:||Cervero, T.
Lopez, J. C.
|UNESCO Clasification:||3307 Tecnología electrónica||Keywords:||Embedded systems Scheduling FPGA Placement Dynamic reconfiguration||Issue Date:||2013||Publisher:||0277-786X||Journal:||Proceedings of SPIE - The International Society for Optical Engineering||Conference:||Conference on VLSI Circuits and Systems VI
6th Conference on VLSI Circuits and Systems
|Abstract:||One of the limiting factors that have prevented a widely dissemination of the reconfigurable technology is the absence of an appropriate model for certain target applications capable of offering a reliable control. Moreover, the lack of flexible and easy-to-use scheduling and management systems are also relevant drawbacks to be considered. Under static scenarios, it is relatively easy to schedule and manage the reconfiguration process since all the variations corresponding to predetermined and well-known tasks. However, the difficulty increases when the adaptation needs of the overall system change semi-randomly according to the environmental fluctuations. In this context, this work proposes a change in the paradigm of dynamically reconfigurable systems, by attending to the dynamically reconfigurable control problematic as a whole, in which the scheduling and the placement issues are packed together as a hierarchical management structure, interacting together as one entity from the system point of view, but performing their tasks with certain degree of independence each other. In this sense, the top hierarchical level corresponds with a dynamic scheduler in charge of planning and adjusting all the reconfigurable modules according to the variations of the external stimulus. The lower level interacts with the physical layer of the device by means of instantiating, relocating, removing a reconfigurable module following the scheduler's instructions.In regards to how fast is the proposed solution, the total partial reconfiguration time achieved with this proposal has been measured and compared with other two approaches: 1) using traditional Xilinx's tools; 2) using an optimized version of the Xilinx's drivers. The collected numbers demonstrate that our solution reaches a gain up to 10 times faster than the other approaches.||URI:||http://hdl.handle.net/10553/44404||ISBN:||9780819495617||ISSN:||0277-786X||DOI:||10.1117/12.2021270||Source:||Proceedings of SPIE - The International Society for Optical Engineering[ISSN 0277-786X],v. 8764 (87640J)|
|Appears in Collections:||Actas de congresos|
checked on Dec 3, 2023
checked on Apr 15, 2023
Items in accedaCRIS are protected by copyright, with all rights reserved, unless otherwise indicated.