|Title:||A resource manager for dynamically reconfigurable FPGA-based embedded systems||Authors:||Cervero, T.
Lopez, J. C.
|UNESCO Clasification:||3307 Tecnología electrónica||Keywords:||Engines , Dynamic scheduling , Field programmable gate arrays , Hardware , Software , Object recognition , Dynamic reconfiguration , FPGA , hierarchical reconfigurable region , reconfiguration engine , scalable design , scheduling||Issue Date:||2013||Journal:||Proceedings - 16th Euromicro Conference on Digital System Design, DSD 2013||Conference:||16th Euromicro Conference on Digital System Design (DSD)
16th Euromicro Conference on Digital System Design, DSD 2013
|Abstract:||FPGA-based embedded systems are gaining relevance for implementing a wide range of applications. Part of their success is due to their balanced compromise between performance and flexibility, but also because of their capability for exploiting the dynamic reconfiguration. However, the costly reconfiguration process and the lack of management support have prevented a broader use of the FPGAs. In order to contribute to solve these issues, in this paper we propose a software/hardware dynamic resource management system that combines scheduling and placement tasks, providing a complete management flow for supporting dynamically reconfigurable hardware designs. One of the advantages of the proposed model is the capability for running its scheduling and placement tasks in different nodes, as part of a distributed network. The results of our experiments demonstrate that our placement policy, specially designed for reconfigurable systems, achieves good results, in terms of reusability and performance, compared to other management approaches.||URI:||http://hdl.handle.net/10553/44402||ISBN:||9780769550749||DOI:||10.1109/DSD.2013.75||Source:||Proceedings - 16th Euromicro Conference on Digital System Design, DSD 2013 (6628336), p. 633-640|
|Appears in Collections:||Actas de congresos|
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