Identificador persistente para citar o vincular este elemento: http://hdl.handle.net/10553/44402
Campo DC Valoridioma
dc.contributor.authorCervero, T.en_US
dc.contributor.authorDondo, J.en_US
dc.contributor.authorGomez, A.en_US
dc.contributor.authorPeña, X.en_US
dc.contributor.authorLopez, S.en_US
dc.contributor.authorRincon, F.en_US
dc.contributor.authorSarmiento, R.en_US
dc.contributor.authorLopez, J. C.en_US
dc.contributor.otherLopez, Sebastian-
dc.contributor.otherDondo Gazzano, Julio-
dc.date.accessioned2018-11-21T22:46:02Z-
dc.date.available2018-11-21T22:46:02Z-
dc.date.issued2013en_US
dc.identifier.isbn9780769550749en_US
dc.identifier.urihttp://hdl.handle.net/10553/44402-
dc.description.abstractFPGA-based embedded systems are gaining relevance for implementing a wide range of applications. Part of their success is due to their balanced compromise between performance and flexibility, but also because of their capability for exploiting the dynamic reconfiguration. However, the costly reconfiguration process and the lack of management support have prevented a broader use of the FPGAs. In order to contribute to solve these issues, in this paper we propose a software/hardware dynamic resource management system that combines scheduling and placement tasks, providing a complete management flow for supporting dynamically reconfigurable hardware designs. One of the advantages of the proposed model is the capability for running its scheduling and placement tasks in different nodes, as part of a distributed network. The results of our experiments demonstrate that our placement policy, specially designed for reconfigurable systems, achieves good results, in terms of reusability and performance, compared to other management approaches.en_US
dc.languagespaen_US
dc.relation.ispartofProceedings - 16th Euromicro Conference on Digital System Design, DSD 2013en_US
dc.sourceProceedings - 16th Euromicro Conference on Digital System Design, DSD 2013 (6628336), p. 633-640en_US
dc.subject3307 Tecnología electrónicaen_US
dc.subject.otherEngines , Dynamic scheduling , Field programmable gate arrays , Hardware , Software , Object recognition , Dynamic reconfiguration , FPGA , hierarchical reconfigurable region , reconfiguration engine , scalable design , schedulingen_US
dc.titleA resource manager for dynamically reconfigurable FPGA-based embedded systemsen_US
dc.typeinfo:eu-repo/semantics/conferenceObjectes
dc.typeConferenceObjectes
dc.relation.conference16th Euromicro Conference on Digital System Design (DSD)
dc.relation.conference16th Euromicro Conference on Digital System Design, DSD 2013
dc.identifier.doi10.1109/DSD.2013.75
dc.identifier.scopus84890088053-
dc.identifier.isi000337235200085-
dcterms.isPartOf16Th Euromicro Conference On Digital System Design (Dsd 2013)-
dcterms.source16Th Euromicro Conference On Digital System Design (Dsd 2013), p. 633-640-
dc.contributor.authorscopusid34978225000-
dc.contributor.authorscopusid24474434400-
dc.contributor.authorscopusid55702521790-
dc.contributor.authorscopusid36457752800-
dc.contributor.authorscopusid57187722000-
dc.contributor.authorscopusid13613157500-
dc.contributor.authorscopusid35609452100-
dc.contributor.authorscopusid55685084700-
dc.description.lastpage640-
dc.identifier.issue6628336-
dc.description.firstpage633-
dc.investigacionIngeniería y Arquitecturaen_US
dc.type2Actas de congresosen_US
dc.identifier.wosWOS:000337235200085-
dc.contributor.daisngid5352902-
dc.contributor.daisngid2345059-
dc.contributor.daisngid22119814-
dc.contributor.daisngid10538600-
dc.contributor.daisngid465777-
dc.contributor.daisngid848261-
dc.contributor.daisngid116294-
dc.contributor.daisngid846472
dc.contributor.daisngid581772-
dc.identifier.investigatorRIDL-8108-2014-
dc.identifier.investigatorRIDNo ID-
dc.identifier.externalWOS:000337235200085-
dc.contributor.wosstandardWOS:Cervero, T
dc.contributor.wosstandardWOS:Dondo, J
dc.contributor.wosstandardWOS:Gomez, A
dc.contributor.wosstandardWOS:Pena, X
dc.contributor.wosstandardWOS:Lopez, S
dc.contributor.wosstandardWOS:Rincon, F
dc.contributor.wosstandardWOS:Sarmiento, R
dc.contributor.wosstandardWOS:Lopez, JC
dc.date.coverdateDiciembre 2013
dc.identifier.conferenceidevents120862
dc.identifier.ulpgces
item.grantfulltextnone-
item.fulltextSin texto completo-
crisitem.author.deptGIR IUMA: Diseño de Sistemas Electrónicos Integrados para el procesamiento de datos-
crisitem.author.deptIU de Microelectrónica Aplicada-
crisitem.author.deptDepartamento de Ingeniería Electrónica y Automática-
crisitem.author.deptGIR IUMA: Diseño de Sistemas Electrónicos Integrados para el procesamiento de datos-
crisitem.author.deptIU de Microelectrónica Aplicada-
crisitem.author.deptDepartamento de Ingeniería Electrónica y Automática-
crisitem.author.deptGIR IUMA: Diseño de Sistemas Electrónicos Integrados para el procesamiento de datos-
crisitem.author.deptIU de Microelectrónica Aplicada-
crisitem.author.deptDepartamento de Ingeniería Electrónica y Automática-
crisitem.author.orcid0000-0002-2360-6721-
crisitem.author.orcid0000-0002-4843-0507-
crisitem.author.orcid0000-0002-2360-6721-
crisitem.author.parentorgIU de Microelectrónica Aplicada-
crisitem.author.parentorgIU de Microelectrónica Aplicada-
crisitem.author.parentorgIU de Microelectrónica Aplicada-
crisitem.author.fullNameCervero García, Teresa Gloria-
crisitem.author.fullNameGómez Rebordinos, Ana-
crisitem.author.fullNameLópez Suárez, Sebastián Miguel-
crisitem.author.fullNameSarmiento Rodríguez, Roberto-
crisitem.author.fullNameLópez Suárez, Sebastián Miguel-
crisitem.event.eventsstartdate04-09-2013-
crisitem.event.eventsstartdate04-09-2013-
crisitem.event.eventsenddate06-09-2013-
crisitem.event.eventsenddate06-09-2013-
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