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Title: Low swing charge recycling driver for on-chip interconnect
Authors: García, José C. 
Montiel-Nelson, Juan A. 
Nooshabadi, Saeid
UNESCO Clasification: 220307 Circuitos integrados
2203 Electrónica
Keywords: Charge recycling technique
Interconnect line
Low power, et al
Issue Date: 2018
Publisher: 1546-1998
Journal: Journal of Low Power Electronics 
Abstract: This paper reviews a number of single voltage supply driver schemes for the on-chip parallel buses in the deep sub-micron CMOS technology, and presents the comprehensive efficiency analysis of delay, and energy that are affected by the coupling capacitance. In addition, we present a new charge recycling (CR) driver scheme structure that achieves a better energy-delay product reduction when connected to a long interconnect line. The performance of each scheme is thoroughly examined using the HSPICE simulation on the benchmark bus circuits. The paper also performs a noise analysis for each schemes. For specific UMC 65 nm CMOS technology, we present a solution which can reduce energy-delay product beyond 15% for interconnect lines longer than 2 mm.
ISSN: 1546-1998
DOI: 10.1166/jolpe.2018.1574
Source: Journal of Low Power Electronics[ISSN 1546-1998],v. 14, p. 428-438
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