Identificador persistente para citar o vincular este elemento: http://hdl.handle.net/10553/42202
Título: Low swing charge recycling driver for on-chip interconnect
Autores/as: García, José C. 
Montiel-Nelson, Juan A. 
Nooshabadi, Saeid
Clasificación UNESCO: 220307 Circuitos integrados
2203 Electrónica
Palabras clave: Charge recycling technique
CMOS
Driver
Interconnect line
Low power, et al.
Fecha de publicación: 2018
Editor/a: 1546-1998
Publicación seriada: Journal of Low Power Electronics 
Resumen: This paper reviews a number of single voltage supply driver schemes for the on-chip parallel buses in the deep sub-micron CMOS technology, and presents the comprehensive efficiency analysis of delay, and energy that are affected by the coupling capacitance. In addition, we present a new charge recycling (CR) driver scheme structure that achieves a better energy-delay product reduction when connected to a long interconnect line. The performance of each scheme is thoroughly examined using the HSPICE simulation on the benchmark bus circuits. The paper also performs a noise analysis for each schemes. For specific UMC 65 nm CMOS technology, we present a solution which can reduce energy-delay product beyond 15% for interconnect lines longer than 2 mm.
URI: http://hdl.handle.net/10553/42202
ISSN: 1546-1998
DOI: 10.1166/jolpe.2018.1574
Fuente: Journal of Low Power Electronics[ISSN 1546-1998],v. 14, p. 428-438
Colección:Artículos
Vista completa

Visitas

47
actualizado el 17-ago-2024

Google ScholarTM

Verifica

Altmetric


Comparte



Exporta metadatos



Los elementos en ULPGC accedaCRIS están protegidos por derechos de autor con todos los derechos reservados, a menos que se indique lo contrario.