Low swing charge recycling driver for on-chip interconnect

Abstract

This paper reviews a number of single voltage supply driver schemes for the on-chip parallel buses in the deep sub-micron CMOS technology, and presents the comprehensive efficiency analysis of delay, and energy that are affected by the coupling capacitance. In addition, we present a new charge recycling (CR) driver scheme structure that achieves a better energy-delay product reduction when connected to a long interconnect line. The performance of each scheme is thoroughly examined using the HSPICE simulation on the benchmark bus circuits. The paper also performs a noise analysis for each schemes. For specific UMC 65 nm CMOS technology, we present a solution which can reduce energy-delay product beyond 15% for interconnect lines longer than 2 mm.