Identificador persistente para citar o vincular este elemento:
http://hdl.handle.net/10553/1744
Campo DC | Valor | idioma |
---|---|---|
dc.contributor.author | Ramírez, Tanausú | en_US |
dc.contributor.author | Pajuelo González, Alejandro | en_US |
dc.contributor.author | Santana, Oliverio J. | en_US |
dc.contributor.author | Valero Cortés, Mateo | en_US |
dc.contributor.other | Departamento de Informática y Sistemas | - |
dc.date.accessioned | 2009-10-08T02:31:00Z | - |
dc.date.accessioned | 2018-03-07T09:00:48Z | - |
dc.date.available | 2018-03-07T09:00:48Z | - |
dc.date.issued | 2006 | en_US |
dc.identifier.isbn | 978-1-59593-302-7 | - |
dc.identifier.issn | 2687-9247 | en_US |
dc.identifier.other | 2034 | - |
dc.identifier.other | Scopus | - |
dc.identifier.uri | http://hdl.handle.net/10553/1744 | - |
dc.description.abstract | There is a continuous research effort devoted to overcome the memory wall problem. Prefetching is one of the most frequently used techniques. A prefetch mechanism anticipates the processor requests by moving data into the lower levels of the memory hierarchy. Runahead mechanism is another form of prefetching based on speculative execution. This mechanism executes speculative instructions under an L2 miss, preventing the processor from being stalled when the reorder buffer completely fills, and thus allowing the generation of useful prefetches. Another technique to alleviate the memory wall problem provides processors with large instruction windows, avoiding window stalls due to in-order commit and long latency loads. This approach, known as “Kilo-instruction processors”, relies on exploiting more instruction level parallelism allowing thousands of inflight instructions while long latency loads are outstanding in memory. In this work, we present a comparative study of the three above-mentioned approaches, showing their key issues and performance tradeoffs. We show that Runahead execution achieves better performance speedups (30% on average) than traditional prefetch techniques (21% on average). Nevertheless, the Kilo-instruction processor performs best (68% on average). Kilo-instruction processors are not only faster but also generate a lower number of speculative instructions than Runahead. When combining the prefetching mechanism evaluated with Runahead and Kilo-instruction processor, the performance is improved even more in each case (49,5% and 88,9% respectively), although Kilo-instruction with prefetch achieves better performance and executes less speculative instructions than Runahead. | en_US |
dc.language | eng | en_US |
dc.relation.ispartof | Proceedings of the ... Conference on Computing Frontiers | en_US |
dc.source | Proceedings of the 3rd Conference on Computing Frontiers 2006, CF '06, [ISSN 2687-9247], 2006, p. 269-278, (Diciembre 2006) | en_US |
dc.subject | 330406 Arquitectura de ordenadores | en_US |
dc.subject.other | Kilo-instruction processors | en_US |
dc.subject.other | Memory wall | en_US |
dc.subject.other | Prefetching | en_US |
dc.subject.other | Runahead | en_US |
dc.subject.other | Speculative execution | en_US |
dc.title | Kilo-instruction processors, runahead and prefetching | en_US |
dc.type | ConferenceObject | en_US |
dc.relation.conference | 3rd Conference on Computing Frontiers 2006, CF '06 | - |
dc.identifier.doi | 10.1145/1128022.1128059 | en_US |
dc.identifier.scopus | 34247374830 | - |
dc.contributor.authorscopusid | Informática y sistemas | - |
dc.contributor.authorscopusid | Informática y sistemas | - |
dc.contributor.authorscopusid | Informática y sistemas | - |
dc.contributor.authorscopusid | 35608297100 | - |
dc.contributor.authorscopusid | 9733817100 | - |
dc.contributor.authorscopusid | 7003605046 | - |
dc.contributor.authorscopusid | 24475914200 | - |
dc.contributor.contentdm | Informática y sistemas | - |
dc.identifier.absysnet | 533719 | - |
dc.description.lastpage | 278 | en_US |
dc.description.firstpage | 269 | en_US |
dc.relation.volume | 2006 | en_US |
dc.investigacion | Ingeniería y Arquitectura | en_US |
dc.rights.accessrights | info:eu-repo/semantics/openAccess | - |
dc.type2 | Actas de congresos | en_US |
dc.utils.revision | Sí | en_US |
dc.contributor.wosstandard | Informática y sistemas | - |
dc.contributor.wosstandard | Informática y sistemas | - |
dc.contributor.wosstandard | Informática y sistemas | - |
dc.contributor.wosstandard | Informática y sistemas | - |
dc.date.coverdate | Diciembre 2006 | en_US |
dc.identifier.conferenceid | events121316 | - |
dc.identifier.ulpgc | Sí | es |
item.grantfulltext | open | - |
item.fulltext | Con texto completo | - |
crisitem.author.dept | GIR SIANI: Inteligencia Artificial, Robótica y Oceanografía Computacional | - |
crisitem.author.dept | IU Sistemas Inteligentes y Aplicaciones Numéricas | - |
crisitem.author.dept | Departamento de Informática y Sistemas | - |
crisitem.author.orcid | 0000-0001-7511-5783 | - |
crisitem.author.parentorg | IU Sistemas Inteligentes y Aplicaciones Numéricas | - |
crisitem.author.fullName | Santana Jaria, Oliverio Jesús | - |
crisitem.event.eventsstartdate | 03-05-2006 | - |
crisitem.event.eventsenddate | 05-05-2006 | - |
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