Please use this identifier to cite or link to this item:
https://accedacris.ulpgc.es/handle/10553/143233
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Gonzalez, Benito | en_US |
dc.contributor.author | Lazaro, Antonio | en_US |
dc.date.accessioned | 2025-07-22T12:16:51Z | - |
dc.date.available | 2025-07-22T12:16:51Z | - |
dc.date.issued | 2025 | en_US |
dc.identifier.issn | 0018-9383 | en_US |
dc.identifier.other | WoS | - |
dc.identifier.uri | https://accedacris.ulpgc.es/handle/10553/143233 | - |
dc.description.abstract | In this article, a new model of the dc drain current in organic electrochemical transistors (OECTs) is developed based on the channel conductivity. For this purpose, a thick-film PEDOT-based OECT was manufactured on a standard FR4 PCB substrate. By making use of the channel capacitance extracted from the ac characteristics, the expected sigmoid function of the gate voltage for the free carrier density is obtained. A bell-shaped dependence on the gate voltage for the carrier mobility is also extracted, with the transistor operating in the linear region and through the Y function method (YFM). Both dependencies combine to give the conductivity, which is obtained from dc measurements and modeled. The drain current is then evaluated using the gradual channel approximation. The channel length modulation effect is incorporated into the model. Good agreement is achieved between the measured and modeled output characteristics of the transistor. In addition, the proposed model predicts the peak in the transconductance and the forward-backward hysteresis curves typically observed in OECTs. The model can be easily implemented in circuit simulators, with the continuity of the transconductance and output conductance between the linear and saturation regions being ensured through a threshold voltage defined as the gate voltage for which the channel conductivity becomes null. | en_US |
dc.language | eng | en_US |
dc.relation.ispartof | IEEE Transactions on Electron Devices | en_US |
dc.source | IEEE Transactions On Electron Devices[ISSN 0018-9383], (2025) | en_US |
dc.subject | 3307 Tecnología electrónica | en_US |
dc.subject.other | Extraction | en_US |
dc.subject.other | Transport | en_US |
dc.subject.other | Device | en_US |
dc.subject.other | Logic Gates | en_US |
dc.subject.other | Capacitance | en_US |
dc.subject.other | Integrated Circuit Modeling | en_US |
dc.subject.other | Electrolytes | en_US |
dc.subject.other | Transconductance | en_US |
dc.subject.other | Mathematical Models | en_US |
dc.subject.other | Transistors | en_US |
dc.subject.other | Resistance | en_US |
dc.subject.other | Threshold Voltage | en_US |
dc.subject.other | Polymers | en_US |
dc.subject.other | Ac Characterization | en_US |
dc.subject.other | Compact Model | en_US |
dc.subject.other | Dc Characterization | en_US |
dc.subject.other | Mobility | en_US |
dc.subject.other | Organic Electrochemical Transistor (Oect) | en_US |
dc.subject.other | Pedot:Pss | en_US |
dc.title | Conductivity-Based DC Model for OECTs | en_US |
dc.type | info:eu-repo/semantics/Article | en_US |
dc.type | Article | en_US |
dc.identifier.doi | 10.1109/TED.2025.3584004 | en_US |
dc.identifier.scopus | 105010003357 | - |
dc.identifier.isi | 001522956300001 | - |
dc.contributor.orcid | 0000-0001-6864-9736 | - |
dc.contributor.orcid | 0000-0003-3160-5777 | - |
dc.contributor.authorscopusid | 56082155300 | - |
dc.contributor.authorscopusid | 56036357200 | - |
dc.identifier.eissn | 1557-9646 | - |
dc.investigacion | Ingeniería y Arquitectura | en_US |
dc.type2 | Artículo | en_US |
dc.contributor.daisngid | No ID | - |
dc.contributor.daisngid | No ID | - |
dc.description.numberofpages | 7 | en_US |
dc.utils.revision | Sí | en_US |
dc.contributor.wosstandard | WOS:González, B | - |
dc.contributor.wosstandard | WOS:Lázaro, A | - |
dc.date.coverdate | 2025 | en_US |
dc.identifier.ulpgc | Sí | en_US |
dc.contributor.buulpgc | BU-TEL | en_US |
dc.description.sjr | 0,785 | - |
dc.description.jcr | 2,9 | - |
dc.description.sjrq | Q1 | - |
dc.description.jcrq | Q2 | - |
dc.description.scie | SCIE | - |
dc.description.miaricds | 11,0 | - |
item.grantfulltext | open | - |
item.fulltext | Con texto completo | - |
crisitem.author.dept | GIR IUMA: Tecnología Microelectrónica | - |
crisitem.author.dept | IU de Microelectrónica Aplicada | - |
crisitem.author.dept | Departamento de Ingeniería Electrónica y Automática | - |
crisitem.author.orcid | 0000-0001-6864-9736 | - |
crisitem.author.parentorg | IU de Microelectrónica Aplicada | - |
crisitem.author.fullName | González Pérez, Benito | - |
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