Please use this identifier to cite or link to this item: https://accedacris.ulpgc.es/handle/10553/143233
DC FieldValueLanguage
dc.contributor.authorGonzalez, Benitoen_US
dc.contributor.authorLazaro, Antonioen_US
dc.date.accessioned2025-07-22T12:16:51Z-
dc.date.available2025-07-22T12:16:51Z-
dc.date.issued2025en_US
dc.identifier.issn0018-9383en_US
dc.identifier.otherWoS-
dc.identifier.urihttps://accedacris.ulpgc.es/handle/10553/143233-
dc.description.abstractIn this article, a new model of the dc drain current in organic electrochemical transistors (OECTs) is developed based on the channel conductivity. For this purpose, a thick-film PEDOT-based OECT was manufactured on a standard FR4 PCB substrate. By making use of the channel capacitance extracted from the ac characteristics, the expected sigmoid function of the gate voltage for the free carrier density is obtained. A bell-shaped dependence on the gate voltage for the carrier mobility is also extracted, with the transistor operating in the linear region and through the Y function method (YFM). Both dependencies combine to give the conductivity, which is obtained from dc measurements and modeled. The drain current is then evaluated using the gradual channel approximation. The channel length modulation effect is incorporated into the model. Good agreement is achieved between the measured and modeled output characteristics of the transistor. In addition, the proposed model predicts the peak in the transconductance and the forward-backward hysteresis curves typically observed in OECTs. The model can be easily implemented in circuit simulators, with the continuity of the transconductance and output conductance between the linear and saturation regions being ensured through a threshold voltage defined as the gate voltage for which the channel conductivity becomes null.en_US
dc.languageengen_US
dc.relation.ispartofIEEE Transactions on Electron Devicesen_US
dc.sourceIEEE Transactions On Electron Devices[ISSN 0018-9383], (2025)en_US
dc.subject3307 Tecnología electrónicaen_US
dc.subject.otherExtractionen_US
dc.subject.otherTransporten_US
dc.subject.otherDeviceen_US
dc.subject.otherLogic Gatesen_US
dc.subject.otherCapacitanceen_US
dc.subject.otherIntegrated Circuit Modelingen_US
dc.subject.otherElectrolytesen_US
dc.subject.otherTransconductanceen_US
dc.subject.otherMathematical Modelsen_US
dc.subject.otherTransistorsen_US
dc.subject.otherResistanceen_US
dc.subject.otherThreshold Voltageen_US
dc.subject.otherPolymersen_US
dc.subject.otherAc Characterizationen_US
dc.subject.otherCompact Modelen_US
dc.subject.otherDc Characterizationen_US
dc.subject.otherMobilityen_US
dc.subject.otherOrganic Electrochemical Transistor (Oect)en_US
dc.subject.otherPedot:Pssen_US
dc.titleConductivity-Based DC Model for OECTsen_US
dc.typeinfo:eu-repo/semantics/Articleen_US
dc.typeArticleen_US
dc.identifier.doi10.1109/TED.2025.3584004en_US
dc.identifier.scopus105010003357-
dc.identifier.isi001522956300001-
dc.contributor.orcid0000-0001-6864-9736-
dc.contributor.orcid0000-0003-3160-5777-
dc.contributor.authorscopusid56082155300-
dc.contributor.authorscopusid56036357200-
dc.identifier.eissn1557-9646-
dc.investigacionIngeniería y Arquitecturaen_US
dc.type2Artículoen_US
dc.contributor.daisngidNo ID-
dc.contributor.daisngidNo ID-
dc.description.numberofpages7en_US
dc.utils.revisionen_US
dc.contributor.wosstandardWOS:González, B-
dc.contributor.wosstandardWOS:Lázaro, A-
dc.date.coverdate2025en_US
dc.identifier.ulpgcen_US
dc.contributor.buulpgcBU-TELen_US
dc.description.sjr0,785-
dc.description.jcr2,9-
dc.description.sjrqQ1-
dc.description.jcrqQ2-
dc.description.scieSCIE-
dc.description.miaricds11,0-
item.grantfulltextopen-
item.fulltextCon texto completo-
crisitem.author.deptGIR IUMA: Tecnología Microelectrónica-
crisitem.author.deptIU de Microelectrónica Aplicada-
crisitem.author.deptDepartamento de Ingeniería Electrónica y Automática-
crisitem.author.orcid0000-0001-6864-9736-
crisitem.author.parentorgIU de Microelectrónica Aplicada-
crisitem.author.fullNameGonzález Pérez, Benito-
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