Low-Power Implementation of a U-Net-based Model for Heart Sound Segmentation on a Low-Cost FPGA

Abstract

This work presents a Field-Programmable Gate Array (FPGA) implementation of a U-Net-based model for heart sound segmentation, building on previous hardware optimization efforts. By converting model parameters to Read-Only Memories instead of Advanced eXtensible Interface (AXI) ports, Block Random Access Memory consumption decreased significantly, from 99% to 58%. Additionally, latency was reduced from 29.27 to 17.66 ms as estimated during High-Level Synthesis (HLS) cosimulation. The U-Net block was integrated into a block design, connected to the Zynq Processing System, facilitating model evaluation on the PYNQ-Z2 board. Model accuracy reached 91.14%, close to HLS C simulation results and high-level Python description. FPGA measured latency was 17.77±0.01 ms, achieving real-time performance, with power consumption estimated at 134±14 mW. Energy per inference was calculated at 2.38±0.07 mJ. A power reduction study showed a 22 % decrease in minimum power consumption compared to default settings, but no significant reduction in energy consumption was observed. This study offers insights for future optimizations, highlighting the applicability of FPGA-based heart sound segmentation in real-world scenarios, and setting the specifications for a potential hand-held device based on this design.