Please use this identifier to cite or link to this item:
https://accedacris.ulpgc.es/handle/10553/128826
DC Field | Value | Language |
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dc.contributor.author | Sánchez Clemente, Antonio José | - |
dc.contributor.author | Barrios Alfaro,Yubal | - |
dc.contributor.author | Santos Falcón, Lucana | - |
dc.contributor.author | Sarmiento Rodríguez, Roberto | - |
dc.date.accessioned | 2024-02-06T17:19:16Z | - |
dc.date.available | 2024-02-06T17:19:16Z | - |
dc.date.issued | 2024 | - |
dc.identifier.issn | 0141-9331 | - |
dc.identifier.other | WoS | - |
dc.identifier.uri | https://accedacris.ulpgc.es/handle/10553/128826 | - |
dc.description.abstract | System-level design makes use of building blocks, known as soft IP cores, to build complex developments. The usage of these IP cores allows to reduce design and verification time, and also to save costs. However, the use of third-party IP cores tends to present difficulties because of a lack of standardization in their organization, distribution and management, which derive in heterogeneous databases. Most of the time, system developers need to describe some additional code to enable the integration, verification and validation of the IP core, which is not available as part of their distribution. This implies acquiring a deep knowledge of each IP core, often with a large learning curve. In this work Abeto is presented, a new software tool for IP core databases management. It allows to easily integrate and use a heterogeneous group of IP cores, described in VHDL, with a unified set of instructions or commands. In order to do so, Abeto requires from every IP core some side information about its packaging and how to operate with the IP. Currently, Abeto provides support for a set of well-known EDA tools and has been successfully applied to the European Space Agency portfolio of IP cores for benchmarking purposes. To demonstrate its performance, mapping results for these IP cores on the novel NanoXplore BRAVE FPGA family are provided. | - |
dc.language | eng | - |
dc.relation | ESA IP Cores Automated Benchmarking | - |
dc.relation.ispartof | Microprocessors and Microsystems | - |
dc.source | Microprocessors and Microsystems [ ISSN 0141-9331], v. 104, 104987, (Febrero 2024) | - |
dc.subject | 120312 Bancos de datos | - |
dc.subject | 33 Ciencias tecnológicas | - |
dc.subject | 3304 Tecnología de los ordenadores | - |
dc.subject.other | Computer aided engineering | - |
dc.subject.other | Electronic design automation | - |
dc.subject.other | Database management | - |
dc.subject.other | IP cores | - |
dc.subject.other | System-level design | - |
dc.title | Abeto: An automated benchmarking tool to manage heterogeneous IP core databases | - |
dc.type | info:eu-repo/semantics/article | - |
dc.type | Article | - |
dc.identifier.doi | 10.1016/j.micpro.2023.104987 | - |
dc.identifier.isi | 001166036800001 | - |
dc.identifier.eissn | 1872-9436 | - |
dc.relation.volume | 104 | - |
dc.investigacion | Ingeniería y Arquitectura | - |
dc.type2 | Artículo | - |
dc.contributor.daisngid | 54813805 | - |
dc.contributor.daisngid | 57795 | - |
dc.contributor.daisngid | 28705473 | - |
dc.contributor.daisngid | 1210220 | - |
dc.description.numberofpages | 9 | - |
dc.utils.revision | Sí | - |
dc.contributor.wosstandard | WOS:Sánchez, AJ | - |
dc.contributor.wosstandard | WOS:Barrios, Y | - |
dc.contributor.wosstandard | WOS:Santos, L | - |
dc.contributor.wosstandard | WOS:Sarmiento, R | - |
dc.date.coverdate | Febrero 2024 | - |
dc.identifier.ulpgc | Sí | - |
dc.contributor.buulpgc | BU-TEL | - |
dc.description.sjr | 0,549 | - |
dc.description.jcr | 1,9 | - |
dc.description.sjrq | Q2 | - |
dc.description.jcrq | Q2 | - |
dc.description.scie | SCIE | - |
dc.description.miaricds | 11,0 | - |
item.fulltext | Con texto completo | - |
item.grantfulltext | open | - |
crisitem.project.principalinvestigator | Sarmiento Rodríguez, Roberto | - |
crisitem.author.dept | GIR IUMA: Diseño de Sistemas Electrónicos Integrados para el procesamiento de datos | - |
crisitem.author.dept | IU de Microelectrónica Aplicada | - |
crisitem.author.dept | GIR IUMA: Diseño de Sistemas Electrónicos Integrados para el procesamiento de datos | - |
crisitem.author.dept | IU de Microelectrónica Aplicada | - |
crisitem.author.dept | GIR IUMA: Diseño de Sistemas Electrónicos Integrados para el procesamiento de datos | - |
crisitem.author.dept | IU de Microelectrónica Aplicada | - |
crisitem.author.dept | Departamento de Ingeniería Electrónica y Automática | - |
crisitem.author.orcid | 0000-0002-2142-7885 | - |
crisitem.author.orcid | 0000-0001-6186-9971 | - |
crisitem.author.orcid | 0000-0002-4843-0507 | - |
crisitem.author.parentorg | IU de Microelectrónica Aplicada | - |
crisitem.author.parentorg | IU de Microelectrónica Aplicada | - |
crisitem.author.parentorg | IU de Microelectrónica Aplicada | - |
crisitem.author.fullName | Sánchez Clemente,Antonio José | - |
crisitem.author.fullName | Barrios Alfaro,Yubal | - |
crisitem.author.fullName | Santos Falcón, Lucana | - |
crisitem.author.fullName | Sarmiento Rodríguez, Roberto | - |
Appears in Collections: | Artículos |
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