Identificador persistente para citar o vincular este elemento: http://hdl.handle.net/10553/114790
Título: FPGA Implementation of the C-Mantec Neural Network Constructive Algorithm
Autores/as: Ortega Zamorano, Francisco 
Jerez, JM
Franco, L
Clasificación UNESCO: 3304 Tecnología de los ordenadores
Palabras clave: Circuit complexity
Constructive neural networks (CoNN)
On-chip learning
Threshold networks
Fecha de publicación: 2014
Publicación seriada: IEEE Transactions on Industrial Informatics 
Resumen: Competitive majority network trained by error correction (C-Mantec), a recently proposed constructive neural network algorithm that generates very compact architectures with good generalization capabilities, is implemented in a field programmable gate array (FPGA). A clear difference with most of the existing neural network implementations (most of them based on the use of the backpropagation algorithm) is that the C-Mantec automatically generates an adequate neural architecture while the training of the data is performed. All the steps involved in the implementation, including the on-chip learning phase, are fully described and a deep analysis of the results is carried on using the two sets of benchmark problems. The results show a clear increase in the computation speed in comparison to the standard personal computer (PC)-based implementation, demonstrating the usefulness of the intrinsic parallelism of FPGAs in the neurocomputational tasks and the suitability of the hardware version of the C-Mantec algorithm for its application to real-world problems. © 2012 IEEE.
URI: http://hdl.handle.net/10553/114790
ISSN: 1551-3203
DOI: 10.1109/TII.2013.2294137
Fuente: IEEE Transactions on Industrial Informatics [ISSN 1551-3203], v. 10(2), p. 1154-1161, (Mayo 2014)
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