Please use this identifier to cite or link to this item: http://hdl.handle.net/10553/114569
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dc.contributor.authorGonzález Pérez, Benitoen_US
dc.contributor.authorCabrera Peña, José Maríaen_US
dc.contributor.authorLazaro, Antonioen_US
dc.date.accessioned2022-05-04T10:05:29Z-
dc.date.available2022-05-04T10:05:29Z-
dc.date.issued2022en_US
dc.identifier.issn0018-9383en_US
dc.identifier.urihttp://hdl.handle.net/10553/114569-
dc.description.abstractThermal impedance is required to describe static and fast dynamic thermal behavior in silicon-oninsulator (SOI) devices. This study presents an empirical physical model, which accounts for gate length, for calculating the thermal impedance of multi-finger partially depleted (PD) SOI MOSFETs at room temperature. For the first time, the parameters of the model are obtained from measurements of ac conductance and the characteristic thermal frequency determination. The model shows decreasing thermal resistance and linearly augmented thermal capacitance with increasing gate length from 0.18 to 2.50 μm. Thus, thermal time constants of ~760 ns, extracted from a variety of gate lengths, are correctly predicted.en_US
dc.languageengen_US
dc.relationNextIOT-RTI2018-096019-B-C31en_US
dc.relation.ispartofIEEE Transactions on Electron Devicesen_US
dc.sourceIEEE Transactions on Electron Devices [ISSN 0018-9383], v. 69 (2), p. 469-474, (Febrero 2022)en_US
dc.subject3307 Tecnología electrónicaen_US
dc.subject.otherElectrothermal characterization modelen_US
dc.subject.otherSilicon-on-insulator (SOI) MOSFETen_US
dc.subject.otherThermal impedanceen_US
dc.titleGate Length-Dependent Thermal Impedance Characterization of PD-SOI MOSFETsen_US
dc.typeinfo:eu-repo/semantics/articleen_US
dc.typeArticleen_US
dc.identifier.doi10.1109/TED.2021.3132854en_US
dc.identifier.scopus2-s2.0-85121806370-
dc.identifier.isiWOS:000733156900001-
dc.contributor.orcid0000-0001-6864-9736-
dc.contributor.orcid#NODATA#-
dc.contributor.orcid0000-0003-3160-5777-
dc.description.lastpage474en_US
dc.identifier.issue2-
dc.description.firstpage469en_US
dc.relation.volume69en_US
dc.investigacionIngeniería y Arquitecturaen_US
dc.type2Artículoen_US
dc.utils.revisionen_US
dc.identifier.ulpgcen_US
dc.contributor.buulpgcBU-TELen_US
dc.description.sjr0,773-
dc.description.jcr3,1-
dc.description.sjrqQ2-
dc.description.jcrqQ2-
dc.description.scieSCIE-
dc.description.miaricds11,0-
item.fulltextCon texto completo-
item.grantfulltextopen-
crisitem.author.deptGIR IUMA: Tecnología Microelectrónica-
crisitem.author.deptIU de Microelectrónica Aplicada-
crisitem.author.deptDepartamento de Ingeniería Electrónica y Automática-
crisitem.author.deptGIR IUMA: Sistemas de Información y Comunicaciones-
crisitem.author.deptIU de Microelectrónica Aplicada-
crisitem.author.deptDepartamento de Ingeniería Electrónica y Automática-
crisitem.author.orcid0000-0001-6864-9736-
crisitem.author.orcid0000-0001-6557-2294-
crisitem.author.parentorgIU de Microelectrónica Aplicada-
crisitem.author.parentorgIU de Microelectrónica Aplicada-
crisitem.author.fullNameGonzález Pérez, Benito-
crisitem.author.fullNameCabrera Peña, José María-
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