Identificador persistente para citar o vincular este elemento: http://hdl.handle.net/10553/112903
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dc.contributor.authorAlbandes, I.en_US
dc.contributor.authorSerrano-Cases, A.en_US
dc.contributor.authorSánchez Clemente, Antonio Joséen_US
dc.contributor.authorMartins, M.en_US
dc.contributor.authorMartinez-Alvarez, A.en_US
dc.contributor.authorCuenca-Asensi, S.en_US
dc.contributor.authorKastensmidt, F. L.en_US
dc.date.accessioned2021-12-10T14:38:10Z-
dc.date.available2021-12-10T14:38:10Z-
dc.date.issued2018en_US
dc.identifier.isbn978-1-5386-1472-3en_US
dc.identifier.urihttp://hdl.handle.net/10553/112903-
dc.description.abstractApproximate Triple Modular Redundancy (ATMR), which is the implementation of TMR with approximate versions of the target circuit, has emerged in recent years as an alternative to partial replication. This work presents a novel approach for implementing approximate TMR that combines an approximate gate library (ApxLib) with a Multi-Objective Optimization Genetic Algorithm (MOOGA). The algorithm initially performs a blind search, over the huge solution space, optimizing error coverage and area overhead altogether over the next interactions. Experiments compare our approach with a state of the art technique showing an improvement of trade-offs for different benchmark circuits.en_US
dc.languageengen_US
dc.publisherInstitute of Electrical and Electronics Engineers (IEEE)en_US
dc.sourceLatin American Test Workshop, LATW, p. 1-6en_US
dc.subject330790 Microelectrónicaen_US
dc.subject.otherApproximate circuitsen_US
dc.subject.otherATMRen_US
dc.subject.otherFault toleranceen_US
dc.subject.otherGenetic algorithmen_US
dc.subject.otherMulti-objective optimizationen_US
dc.titleImproving approximate-TMR using multi-objective optimization genetic algorithmen_US
dc.typeinfo:eu-repo/semantics/conferenceObjecten_US
dc.typeconferenceObjecten_US
dc.relation.conference19th Latin-American Test Symposium (LATS 2018)en_US
dc.identifier.doi10.1109/LATW.2018.8349665en_US
dc.identifier.scopus2-s2.0-85050923797-
dc.contributor.orcid#NODATA#-
dc.contributor.orcid#NODATA#-
dc.contributor.orcid#NODATA#-
dc.contributor.orcid#NODATA#-
dc.contributor.orcid#NODATA#-
dc.contributor.orcid#NODATA#-
dc.contributor.orcid#NODATA#-
dc.investigacionIngeniería y Arquitecturaen_US
dc.type2Actas de congresosen_US
dc.identifier.eisbn978-1-5386-1471-6-
dc.utils.revisionen_US
dc.identifier.ulpgcNoen_US
dc.contributor.buulpgcBU-INGen_US
item.fulltextSin texto completo-
item.grantfulltextnone-
crisitem.event.eventsstartdate12-03-2018-
crisitem.event.eventsenddate14-03-2018-
crisitem.author.deptGIR IUMA: Diseño de Sistemas Electrónicos Integrados para el procesamiento de datos-
crisitem.author.deptIU de Microelectrónica Aplicada-
crisitem.author.orcid0000-0002-2142-7885-
crisitem.author.parentorgIU de Microelectrónica Aplicada-
crisitem.author.fullNameSánchez Clemente,Antonio José-
Colección:Actas de congresos
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