Please use this identifier to cite or link to this item:
http://hdl.handle.net/10553/112903
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Albandes, I. | en_US |
dc.contributor.author | Serrano-Cases, A. | en_US |
dc.contributor.author | Sánchez Clemente, Antonio José | en_US |
dc.contributor.author | Martins, M. | en_US |
dc.contributor.author | Martinez-Alvarez, A. | en_US |
dc.contributor.author | Cuenca-Asensi, S. | en_US |
dc.contributor.author | Kastensmidt, F. L. | en_US |
dc.date.accessioned | 2021-12-10T14:38:10Z | - |
dc.date.available | 2021-12-10T14:38:10Z | - |
dc.date.issued | 2018 | en_US |
dc.identifier.isbn | 978-1-5386-1472-3 | en_US |
dc.identifier.uri | http://hdl.handle.net/10553/112903 | - |
dc.description.abstract | Approximate Triple Modular Redundancy (ATMR), which is the implementation of TMR with approximate versions of the target circuit, has emerged in recent years as an alternative to partial replication. This work presents a novel approach for implementing approximate TMR that combines an approximate gate library (ApxLib) with a Multi-Objective Optimization Genetic Algorithm (MOOGA). The algorithm initially performs a blind search, over the huge solution space, optimizing error coverage and area overhead altogether over the next interactions. Experiments compare our approach with a state of the art technique showing an improvement of trade-offs for different benchmark circuits. | en_US |
dc.language | eng | en_US |
dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) | en_US |
dc.source | Latin American Test Workshop, LATW, p. 1-6 | en_US |
dc.subject | 330790 Microelectrónica | en_US |
dc.subject.other | Approximate circuits | en_US |
dc.subject.other | ATMR | en_US |
dc.subject.other | Fault tolerance | en_US |
dc.subject.other | Genetic algorithm | en_US |
dc.subject.other | Multi-objective optimization | en_US |
dc.title | Improving approximate-TMR using multi-objective optimization genetic algorithm | en_US |
dc.type | info:eu-repo/semantics/conferenceObject | en_US |
dc.type | conferenceObject | en_US |
dc.relation.conference | 19th Latin-American Test Symposium (LATS 2018) | en_US |
dc.identifier.doi | 10.1109/LATW.2018.8349665 | en_US |
dc.identifier.scopus | 2-s2.0-85050923797 | - |
dc.contributor.orcid | #NODATA# | - |
dc.contributor.orcid | #NODATA# | - |
dc.contributor.orcid | #NODATA# | - |
dc.contributor.orcid | #NODATA# | - |
dc.contributor.orcid | #NODATA# | - |
dc.contributor.orcid | #NODATA# | - |
dc.contributor.orcid | #NODATA# | - |
dc.investigacion | Ingeniería y Arquitectura | en_US |
dc.type2 | Actas de congresos | en_US |
dc.identifier.eisbn | 978-1-5386-1471-6 | - |
dc.utils.revision | Sí | en_US |
dc.identifier.ulpgc | No | en_US |
dc.contributor.buulpgc | BU-ING | en_US |
item.fulltext | Sin texto completo | - |
item.grantfulltext | none | - |
crisitem.event.eventsstartdate | 12-03-2018 | - |
crisitem.event.eventsenddate | 14-03-2018 | - |
crisitem.author.dept | GIR IUMA: Diseño de Sistemas Electrónicos Integrados para el procesamiento de datos | - |
crisitem.author.dept | IU de Microelectrónica Aplicada | - |
crisitem.author.orcid | 0000-0002-2142-7885 | - |
crisitem.author.parentorg | IU de Microelectrónica Aplicada | - |
crisitem.author.fullName | Sánchez Clemente,Antonio José | - |
Appears in Collections: | Actas de congresos |
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