Dynamically reconfigurable architectures for video coding and hyperspectral imaging systems

Abstract

Los sistemas empotrados basados en FPGAs están cobrando mayor relevancia en un amplio número de aplicaciones. Parte del éxito de las FPGAs se debe al equilibrio entre flexibilidad y rendimiento pero también a su capacidad para ser reconfiguradas dinámicamente. Esta Tesis doctoral tiene por objetivo explorar las ventajas que ofrece el desarrollo de sistemas escalables, dentro del campo de la reconfiguración dinámica. Para ello se proponen un conjunto de arquitecturas hardware escalables para dos aplicaciones de alto rendimiento bien distintas entre sí: codificación de vídeo y desmezclado hiperespectral lineal. Para el control del proceso de reconfiguración, también se propone un elemento flexible de control y gestión llamado DRM, y más específicamente se centra en el planificador, con el fin de llenar el vacío existente en el desarrollo de sistemas empotrados basados en FPGAs.

FPGA-based embedded systems are gaining relevance for implementing a wide range of applications. Part of this success is due to their balanced compromise between performance and flexibility, but also because of their capability for exploiting the dynamic reconfigurability. First of all, in order to study the possible positive or negative effects derived from adapting the performance of an application dynamically, this Thesis pro-poses a set of scalable hardware architectures for two high performance but very different applications: video coding and hyperspectral linear unmixing. However, despite the fact that these hardware solutions might be scaled dy-namically, they do not incorporate any mechanism for being reconfigured by themselves. In fact, the reconfiguration management must be supervised by another mechanism. Therefore, with the objective of alleviating this fact, this Thesis also proposes a flexible module for controlling, managing and checking the dynamic reconfigurability procedure. As a whole, these contributions (the scalable designs and the reconfigurability mechanism) are focused on filling the gap in the development of FPGA-based context-aware embedded systems.