Please use this identifier to cite or link to this item: http://hdl.handle.net/10553/110297
Title: Hardware/Software partitioning based on Simulated Annealing
Authors: Sánchez Rodríguez, David Cruz 
Catellano, Juan
Suárez Sarmiento, Álvaro 
UNESCO Clasification: 3325 Tecnología de las telecomunicaciones
Issue Date: 2000
Publisher: Universidad de Las Palmas de Gran Canaria (ULPGC) 
Conference: International Conference on Modelling and Simulation (MS'2000) 
Abstract: A software implementation often can not satisfy embedded systems timing constraints. This problem can be solved by adding specifíc hardware to the system. Lately, it has been developed some design methodologies for this type of hardware/software systems. Our research group is developing a hardware/ software codesign environment for designing this type of systems. In this paper, we present our Hw/Sw partitioning algorithm that is based on simulated annealing. Main contribution is the foUowing: it supports process-level pipelining and estimates system power consumption. Thus, system designer can explore the design space to make latency, área and power trade-offs.
URI: http://hdl.handle.net/10553/110297
ISBN: 84-95286-59-9
Source: Proceedings of MS'2000 international conference on modelling and simulation / Ed. Rosario Berriel Martínez, p. 115-122
Appears in Collections:Actas de congresos
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