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Title: HLS code refactoring using SDSoC applied to multiclass SVM classification of Hyperspectral Images
Authors: Báez Quevedo, Abelardo 
Fabelo Gómez, Himar Antonio 
Ortega Sarmiento, Samuel 
Marrero Callicó, Gustavo Iván 
Sarmiento Rodríguez, Roberto 
UNESCO Clasification: 220990 Tratamiento digital. Imágenes
Keywords: High-Level Synthesis
Support vector mcahines
SVM, et al
Issue Date: 2019
Project: Plataforma H2/Sw Distribuida Para El Procesamiento Inteligente de Información Sensorial Heterogenea en Aplicaciones de Supervisión de Grandes Espacios Naturales 
Identificación Hiperespectral de Tumores Cerebrales (Ithaca) 
Conference: 34th Conference on Design of Circuits and Integrated Systems, DCIS 2019 
Abstract: Nowadays, High-Level Synthesis (HLS) methods and tools are a highly relevant area in the strategy of several leading companies in the field of System on Chips (SoCs) and Field Programmable Gate Arrays (FPGAs). HLS allows FPGA manufactures to widen the target market, smoothing the existing barriers that prevented potential users from adopting reconfigurable hardware technologies and easing the work of system developers, who benefit from integrated and automated design workflows, considerably reducing the “time to market” constrain. On the other hand, although many advances have been made in this research field, there are some uncertainties about the quality and performance of the designs that results from the use of HLS processes. Since HLS tools increase the level of abstraction, it is necessary to evaluate if the possible performance losses compensate the design time reduction. For these reasons, it is highly important to know how to write efficient code for HLS tools, being mandatory a good understanding of the HLS methods to achieve the best results. In this paper, an optimization of the HLS methodology by code refactoring using SDSoCTM (Software-Defined System-On-Chip) is presented. Several options were analyzed for each alternative through the code refactoring of a multiclass Support Vector Machine (SVM) classifier written in C, using the programmable logic of a Zynq®-7000 SoC device by Xilinx. Thus, a quantitative evaluation of the results achieved is presented order to provide designers with a methodology that will speed up their implementations
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