Identificador persistente para citar o vincular este elemento:
http://hdl.handle.net/10553/45034
| Título: | An efficient architecture for hardware implementation of H.264/AVC deblocking filtering | Autores/as: | Tobajas, Felix Callicó, Gustavo Pérez, Pedro A. De Armas Sosa, Valentín Sarmiento, Roberto |
Clasificación UNESCO: | 3307 Tecnología electrónica | Palabras clave: | Automatic voltage control Read-write memory Filtering Adaptive filters Video sequences, et al. |
Fecha de publicación: | 2008 | Publicación seriada: | Digest of Technical Papers - IEEE International Conference on Consumer Electronics | Conferencia: | 26th IEEE International Conference on Consumer Electronics 26th IEEE International Conference on Consumer Electronics, The Mobile Consumer, ICCE 2008 |
Resumen: | In this paper, a novel hardware architecture for real-time implementation of the adaptive deblocking filtering process specified by the H.264/AVC standard, is presented. The proposed architecture is based on a double-filter strategy that results in a significant saving in filtering cycles, memory requirements and gate count when compared with state-of-the-art approaches. | URI: | http://hdl.handle.net/10553/45034 | ISBN: | 978-1-4244-1458-1 142441458X |
ISSN: | 0747-668X | DOI: | 10.1109/ICCE.2008.4588056 | Fuente: | Digest of Technical Papers - IEEE International Conference on Consumer Electronics[ISSN 0747-668X] (4588056) |
| Colección: | Actas de congresos |
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