Identificador persistente para citar o vincular este elemento: http://hdl.handle.net/10553/75504
Campo DC Valoridioma
dc.contributor.authorAranda, Luis Albertoen_US
dc.contributor.authorSánchez Clemente, Antonio Joséen_US
dc.contributor.authorGarcia-Herrero, Franciscoen_US
dc.contributor.authorBarrios Alfaro, Yubalen_US
dc.contributor.authorSarmiento, Robertoen_US
dc.contributor.authorMaestro, Juan Antonioen_US
dc.date.accessioned2020-11-13T08:38:43Z-
dc.date.available2020-11-13T08:38:43Z-
dc.date.issued2020en_US
dc.identifier.issn2079-9292en_US
dc.identifier.otherScopus-
dc.identifier.urihttp://hdl.handle.net/10553/75504-
dc.description.abstractHyperspectral images can comprise hundreds of spectral bands, which means that they can represent a large volume of data difficult to manage with the available on-board resources. Lossless compression solutions are interesting for reducing the amount of information stored or transmitted while preserving it at the same time. The Hyperspectral Lossless Compressor for space applications (SHyLoC), which is part of the European Space Agency (ESA) IP core’s library, has been demonstrated to meet the requirements of space missions in terms of compression efficiency, low complexity and high throughput. Currently, there is a trend to use Commercial Off-The-Shelf (COTS) on-board electronic devices on small satellites. Moreover, commercial Field-Programmable Gate Arrays (FPGAs) have been used in a number of them. Hence, a reliability analysis is required to ensure the robustness of the applications to Single Event Upsets (SEUs) in the configuration memory. In this work, we present a reliability analysis of this hyperspectral image compression module as a first step towards the development of ad-hoc fault-tolerant protection techniques for the SHyLoC IP core. The reliability analysis is performed using a fault-injection-based experimental set-up in which a hardware implementation of the Consultative Committee for Space Data Systems (CCSDS) 123.0-B-1 lossless compression standard is tested against configuration memory errors in a Xilinx Zynq XC7Z020 System-on-Chip. The results obtained for unhardened and redundancy-based protected versions of the module are put into perspective in terms of area/power consumption and availability/protection coverage gained to provide insight into the development of more efficient knowledge-based protection schemes.en_US
dc.languageengen_US
dc.relation.ispartofElectronics (Switzerland)en_US
dc.sourceElectronics (Switzerland) [EISSN 2079-9292], v. 9 (10), 1681, (Octubre 2020)en_US
dc.subject3307 Tecnología electrónicaen_US
dc.subject.otherFault Injectionen_US
dc.subject.otherFPGAen_US
dc.subject.otherHyperspectral Image Compressionen_US
dc.subject.otherReliabilityen_US
dc.subject.otherSoft Errorsen_US
dc.titleReliability analysis of the shyloc ccsds123 ip core for lossless hyperspectral image compression using cots FPGAsen_US
dc.typeinfo:eu-repo/semantics/Articleen_US
dc.typeArticleen_US
dc.identifier.doi10.3390/electronics9101681en_US
dc.identifier.scopus85092553601-
dc.contributor.authorscopusid57194725301-
dc.contributor.authorscopusid57211429595-
dc.contributor.authorscopusid53877344900-
dc.contributor.authorscopusid57201297173-
dc.contributor.authorscopusid35609452100-
dc.contributor.authorscopusid8664715000-
dc.identifier.eissn2079-9292-
dc.description.lastpage15en_US
dc.identifier.issue10-
dc.description.firstpage1en_US
dc.relation.volume9en_US
dc.investigacionIngeniería y Arquitecturaen_US
dc.type2Artículoen_US
dc.description.notasThis article belongs to the Special Issue Hardware Architectures for Real Time Image Processingen_US
dc.utils.revisionen_US
dc.identifier.ulpgcen_US
dc.contributor.buulpgcBU-TELen_US
dc.description.sjr0,36
dc.description.jcr2,397
dc.description.sjrqQ2
dc.description.jcrqQ3
dc.description.scieSCIE
item.grantfulltextopen-
item.fulltextCon texto completo-
crisitem.author.deptGIR IUMA: Diseño de Sistemas Electrónicos Integrados para el procesamiento de datos-
crisitem.author.deptIU de Microelectrónica Aplicada-
crisitem.author.deptGIR IUMA: Diseño de Sistemas Electrónicos Integrados para el procesamiento de datos-
crisitem.author.deptIU de Microelectrónica Aplicada-
crisitem.author.deptGIR IUMA: Diseño de Sistemas Electrónicos Integrados para el procesamiento de datos-
crisitem.author.deptIU de Microelectrónica Aplicada-
crisitem.author.deptDepartamento de Ingeniería Electrónica y Automática-
crisitem.author.orcid0000-0002-2142-7885-
crisitem.author.orcid0000-0001-6186-9971-
crisitem.author.orcid0000-0002-4843-0507-
crisitem.author.parentorgIU de Microelectrónica Aplicada-
crisitem.author.parentorgIU de Microelectrónica Aplicada-
crisitem.author.parentorgIU de Microelectrónica Aplicada-
crisitem.author.fullNameSánchez Clemente, Antonio José-
crisitem.author.fullNameBarrios Alfaro,Yubal-
crisitem.author.fullNameSarmiento Rodríguez, Roberto-
Colección:Artículos
miniatura
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