Identificador persistente para citar o vincular este elemento:
http://hdl.handle.net/10553/75504
Campo DC | Valor | idioma |
---|---|---|
dc.contributor.author | Aranda, Luis Alberto | en_US |
dc.contributor.author | Sánchez Clemente, Antonio José | en_US |
dc.contributor.author | Garcia-Herrero, Francisco | en_US |
dc.contributor.author | Barrios Alfaro, Yubal | en_US |
dc.contributor.author | Sarmiento, Roberto | en_US |
dc.contributor.author | Maestro, Juan Antonio | en_US |
dc.date.accessioned | 2020-11-13T08:38:43Z | - |
dc.date.available | 2020-11-13T08:38:43Z | - |
dc.date.issued | 2020 | en_US |
dc.identifier.issn | 2079-9292 | en_US |
dc.identifier.other | Scopus | - |
dc.identifier.uri | http://hdl.handle.net/10553/75504 | - |
dc.description.abstract | Hyperspectral images can comprise hundreds of spectral bands, which means that they can represent a large volume of data difficult to manage with the available on-board resources. Lossless compression solutions are interesting for reducing the amount of information stored or transmitted while preserving it at the same time. The Hyperspectral Lossless Compressor for space applications (SHyLoC), which is part of the European Space Agency (ESA) IP core’s library, has been demonstrated to meet the requirements of space missions in terms of compression efficiency, low complexity and high throughput. Currently, there is a trend to use Commercial Off-The-Shelf (COTS) on-board electronic devices on small satellites. Moreover, commercial Field-Programmable Gate Arrays (FPGAs) have been used in a number of them. Hence, a reliability analysis is required to ensure the robustness of the applications to Single Event Upsets (SEUs) in the configuration memory. In this work, we present a reliability analysis of this hyperspectral image compression module as a first step towards the development of ad-hoc fault-tolerant protection techniques for the SHyLoC IP core. The reliability analysis is performed using a fault-injection-based experimental set-up in which a hardware implementation of the Consultative Committee for Space Data Systems (CCSDS) 123.0-B-1 lossless compression standard is tested against configuration memory errors in a Xilinx Zynq XC7Z020 System-on-Chip. The results obtained for unhardened and redundancy-based protected versions of the module are put into perspective in terms of area/power consumption and availability/protection coverage gained to provide insight into the development of more efficient knowledge-based protection schemes. | en_US |
dc.language | eng | en_US |
dc.relation.ispartof | Electronics (Switzerland) | en_US |
dc.source | Electronics (Switzerland) [EISSN 2079-9292], v. 9 (10), 1681, (Octubre 2020) | en_US |
dc.subject | 3307 Tecnología electrónica | en_US |
dc.subject.other | Fault Injection | en_US |
dc.subject.other | FPGA | en_US |
dc.subject.other | Hyperspectral Image Compression | en_US |
dc.subject.other | Reliability | en_US |
dc.subject.other | Soft Errors | en_US |
dc.title | Reliability analysis of the shyloc ccsds123 ip core for lossless hyperspectral image compression using cots FPGAs | en_US |
dc.type | info:eu-repo/semantics/Article | en_US |
dc.type | Article | en_US |
dc.identifier.doi | 10.3390/electronics9101681 | en_US |
dc.identifier.scopus | 85092553601 | - |
dc.contributor.authorscopusid | 57194725301 | - |
dc.contributor.authorscopusid | 57211429595 | - |
dc.contributor.authorscopusid | 53877344900 | - |
dc.contributor.authorscopusid | 57201297173 | - |
dc.contributor.authorscopusid | 35609452100 | - |
dc.contributor.authorscopusid | 8664715000 | - |
dc.identifier.eissn | 2079-9292 | - |
dc.description.lastpage | 15 | en_US |
dc.identifier.issue | 10 | - |
dc.description.firstpage | 1 | en_US |
dc.relation.volume | 9 | en_US |
dc.investigacion | Ingeniería y Arquitectura | en_US |
dc.type2 | Artículo | en_US |
dc.description.notas | This article belongs to the Special Issue Hardware Architectures for Real Time Image Processing | en_US |
dc.utils.revision | Sí | en_US |
dc.identifier.ulpgc | Sí | en_US |
dc.contributor.buulpgc | BU-TEL | en_US |
dc.description.sjr | 0,36 | |
dc.description.jcr | 2,397 | |
dc.description.sjrq | Q2 | |
dc.description.jcrq | Q3 | |
dc.description.scie | SCIE | |
item.grantfulltext | open | - |
item.fulltext | Con texto completo | - |
crisitem.author.dept | GIR IUMA: Diseño de Sistemas Electrónicos Integrados para el procesamiento de datos | - |
crisitem.author.dept | IU de Microelectrónica Aplicada | - |
crisitem.author.dept | GIR IUMA: Diseño de Sistemas Electrónicos Integrados para el procesamiento de datos | - |
crisitem.author.dept | IU de Microelectrónica Aplicada | - |
crisitem.author.dept | GIR IUMA: Diseño de Sistemas Electrónicos Integrados para el procesamiento de datos | - |
crisitem.author.dept | IU de Microelectrónica Aplicada | - |
crisitem.author.dept | Departamento de Ingeniería Electrónica y Automática | - |
crisitem.author.orcid | 0000-0002-2142-7885 | - |
crisitem.author.orcid | 0000-0001-6186-9971 | - |
crisitem.author.orcid | 0000-0002-4843-0507 | - |
crisitem.author.parentorg | IU de Microelectrónica Aplicada | - |
crisitem.author.parentorg | IU de Microelectrónica Aplicada | - |
crisitem.author.parentorg | IU de Microelectrónica Aplicada | - |
crisitem.author.fullName | Sánchez Clemente, Antonio José | - |
crisitem.author.fullName | Barrios Alfaro,Yubal | - |
crisitem.author.fullName | Sarmiento Rodríguez, Roberto | - |
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