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http://hdl.handle.net/10553/75353
Title: | Lossy hyperspectral image compression on a reconfigurable and fault-tolerant fpga-based adaptive computing platform† | Authors: | Barrios Alfaro, Yubal Rodríguez, Alfonso Sánchez Clemente, Antonio José Pérez, Arturo López, Sebastián Otero, Andrés de la Torre, Eduardo Sarmiento, Roberto |
UNESCO Clasification: | 3307 Tecnología electrónica | Keywords: | Ccsds Fault-Tolerance Hardware Acceleration Hyperspectral Imaging Lossy Data Compression, et al |
Issue Date: | 2020 | Journal: | Electronics (Switzerland) | Abstract: | This paper describes a novel hardware implementation of a lossy multispectral and hyperspectral image compressor for on-board operation in space missions. The compression algorithm is a lossy extension of the Consultative Committee for Space Data Systems (CCSDS) 123.0-B-1 lossless standard that includes a bit-rate control stage, which in turn manages the losses the compressor may introduce to achieve higher compression ratios without compromising the recovered image quality. The algorithm has been implemented using High-Level Synthesis (HLS) techniques to increase design productivity by raising the abstraction level. The proposed lossy compression solution is deployed onto ARTICo3, a dynamically reconfigurable multi-accelerator architecture, obtaining a run-time adaptive solution that enables user-selectable performance (i.e., load more hardware accelerators to transparently increase throughput), power consumption, and fault tolerance (i.e., group hardware accelerators to transparently enable hardware redundancy). The whole compression solution is tested on a Xilinx Zynq UltraScale+ Field-Programmable Gate Array (FPGA)-based MPSoC using different input images, from multispectral to ultraspectral. For images acquired by the Airborne Visible/Infrared Imaging Spectrometer (AVIRIS), the proposed implementation renders an execution time of approximately 36 s when 8 accelerators are compressing concurrently at 100 MHz, which in turn uses around 20% of the LUTs and 17% of the dedicated memory blocks available in the target device. In this scenario, a speedup of 15.6× is obtained in comparison with a pure software version of the algorithm running in an ARM Cortex-A53 processor. | URI: | http://hdl.handle.net/10553/75353 | DOI: | 10.3390/electronics9101576 | Source: | Electronics (Switzerland)[EISSN 2079-9292],v. 9 (10), p. 1-23, (Octubre 2020) |
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