|Title:||Quantitative Modelling of Image Processing Algorithms for Hardware Implementation||Authors:||Szydzik, Tomasz
Callico, Gustavo M.
|UNESCO Clasification:||220990 Tratamiento digital. Imágenes||Keywords:||Modelling
Communications Traffic Evaluation
Memory Requirements Reduction Trade Offs
|Issue Date:||2016||Journal:||Proceedings (Conference on Design of Circuits and Integrated Systems)||Conference:||2015 Conference on Design of Circuits and Integrated Systems (DCIS)||Abstract:||Availability of hardware implementations of super-resolution image reconstruction algorithms is limited mostly by their logical and memory requirements. This is also the case for other image processing algorithms such as hyperspectral, image compression, image coding, video coding. In previous publications we have introduced a new execution flow that tackles the problem of high memory requirements of a restoration-interpolation super-resolution kernel by carrying out processing in a macroblock-by-macroblock manner. In this work we present the modelling framework used for the evaluation of the proposed execution flow. The modelling process is presented in a step-by-step manner by means of a real-life example of implementation of super-resolution image reconstruction with description of the choices made at every stage and explanation of the reasoning behind. In the presented case the use of the proposed frame-work led to a hardware implementation with real-time capabilities. This frame-work can be applied to similar algorithms, helping system designers in achieving better work organization and efficiency.||URI:||http://hdl.handle.net/10553/74438||ISBN:||9781467372282||ISSN:||2471-6170||DOI:||10.1109/DCIS.2015.7388569||Source:||2015 Conference on Design of Circuits And Integrated Systems (DCIS) [ISSN 2471-6170], 7388569, (2015)|
|Appears in Collections:||Actas de congresos|
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