Please use this identifier to cite or link to this item: http://hdl.handle.net/10553/72794
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dc.contributor.authorBenítez, Domingoen_US
dc.date.accessioned2020-05-27T20:43:23Z-
dc.date.available2020-05-27T20:43:23Z-
dc.date.issued2002en_US
dc.identifier.isbn978-0-7695-1790-2en_US
dc.identifier.isbn0-7695-1790-0-
dc.identifier.otherWoS-
dc.identifier.otherScopus-
dc.identifier.urihttp://hdl.handle.net/10553/72794-
dc.description.abstractThis paper describes a performance evaluation of Image-Processing applications on FPGA-based coprocessors that are part of general-purpose computers. Our experiments show that the maximum speed-up depends on the amount of data processed by the coprocessor. Taking images with 256 x 256 pixels, a moderate FPGA capacity of 10E+5 CLBs provides two orders of magnitude of performance, improvement over a Pentium III processor for most of our benchmarks. However, memory organization and host bus degrade these results. Those benchmarks that can exhibit high performance improvement would require about 200 memory banks of 256 bytes and a host bandwidth as high as 30 GB/s. Based on our quantitative approach, it can be explained why some currently available FPGA-based coprocessors do not provide the achievable level of performance for some Image-Processing applications.en_US
dc.languageengen_US
dc.sourceProceedings - Euromicro Symposium on Digital System Design: Architectures, Methods and Tools, DSD 2002, p. 268-275, (Enero 2002)en_US
dc.subject1203 Ciencia de los ordenadoresen_US
dc.subject.otherArchitectureen_US
dc.subject.otherMultimediaen_US
dc.subject.otherPiperenchen_US
dc.subject.otherCompileren_US
dc.subject.otherSystemsen_US
dc.titlePerformance of remote FPGA-based coprocessors for image-processing applicationsen_US
dc.typeinfo:eu-repo/semantics/conferenceObjecten_US
dc.typeConferenceObjecten_US
dc.relation.conferenceJoint Meeting of the 28th EUROMICRO Conference/EUROMICRO Symposium on Digital System Designen_US
dc.identifier.doi10.1109/DSD.2002.1115378en_US
dc.identifier.scopus41149137907-
dc.identifier.isi000178310200035-
dc.contributor.authorscopusid7003286582-
dc.description.lastpage275en_US
dc.description.firstpage268en_US
dc.investigacionIngeniería y Arquitecturaen_US
dc.type2Actas de congresosen_US
dc.contributor.daisngid21603236-
dc.description.numberofpages8en_US
dc.utils.revisionen_US
dc.contributor.wosstandardWOS:Benitez, D-
dc.date.coverdate2002en_US
dc.identifier.conferenceidevents120327-
dc.identifier.ulpgces
item.fulltextSin texto completo-
item.grantfulltextnone-
crisitem.event.eventsstartdate04-09-2002-
crisitem.event.eventsenddate06-09-2002-
crisitem.author.deptGIR SIANI: Modelización y Simulación Computacional-
crisitem.author.deptIU Sistemas Inteligentes y Aplicaciones Numéricas-
crisitem.author.deptDepartamento de Informática y Sistemas-
crisitem.author.orcid0000-0003-2952-2972-
crisitem.author.parentorgIU Sistemas Inteligentes y Aplicaciones Numéricas-
crisitem.author.fullNameBenítez Díaz, Domingo Juan-
Appears in Collections:Actas de congresos
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