Please use this identifier to cite or link to this item: http://hdl.handle.net/10553/72739
Title: Predictable performance in SMT processors: synergy between the OS and SMTs
Authors: Cazorla, Francisco J.
Knijnenburg, Peter M. W.
Sakellariou, Rizos
Fernandez, Enrique 
Ramirez, Alex 
Valero, Mateo
UNESCO Clasification: 1203 Ciencia de los ordenadores
330406 Arquitectura de ordenadores
120324 Teoría de la programación
Keywords: Multithreaded processors
Simultaneous multithreading
Ilp
Thread-level parallelism
Performance predictability
Real time
Operating systems
Issue Date: 2006
Journal: IEEE Transactions on Computers 
Abstract: Current Operating Systems ( OS) perceive the different contexts of Simultaneous Multithreaded (SMT) processors as multiple independent processing units, although, in reality, threads executed in these units compete for the same hardware resources. Furthermore, hardware resources are assigned to threads implicitly as determined by the SMT instruction fetch (Ifetch) policy, without the control of the OS. Both factors cause a lack of control over how individual threads are executed, which can frustrate the work of the job scheduler. This presents a problem for general purpose systems, where the OS job scheduler cannot enforce priorities, and also for embedded systems, where it would be difficult to guarantee worst-case execution times. In this paper, we propose a novel strategy that enables a two-way interaction between the OS and the SMT processor and allows the OS to run jobs at a certain percentage of their maximum speed, regardless of the workload in which these jobs are executed. In contrast to previous approaches, our approach enables the OS to run time-critical jobs without dedicating all internal resources to them so that non-time-critical jobs can make significant progress as well and without significantly compromising overall throughput. In fact, our mechanism, in addition to fulfilling OS requirements, achieves 90 precent of the throughput of one of the best currently known fetch policies for SMTs.
URI: http://hdl.handle.net/10553/72739
ISSN: 0018-9340
DOI: 10.1109/TC.2006.108
Source: IEEE Transactions On Computers [ISSN 0018-9340], v. 55 (7), p. 785-799, (Julio 2006)
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