Identificador persistente para citar o vincular este elemento: http://hdl.handle.net/10553/72739
Campo DC Valoridioma
dc.contributor.authorCazorla, Francisco J.en_US
dc.contributor.authorKnijnenburg, Peter M. W.en_US
dc.contributor.authorSakellariou, Rizosen_US
dc.contributor.authorFernandez, Enriqueen_US
dc.contributor.authorRamirez, Alexen_US
dc.contributor.authorValero, Mateoen_US
dc.date.accessioned2020-05-22T12:02:42Z-
dc.date.available2020-05-22T12:02:42Z-
dc.date.issued2006en_US
dc.identifier.issn0018-9340en_US
dc.identifier.otherWoS-
dc.identifier.urihttp://hdl.handle.net/10553/72739-
dc.description.abstractCurrent Operating Systems ( OS) perceive the different contexts of Simultaneous Multithreaded (SMT) processors as multiple independent processing units, although, in reality, threads executed in these units compete for the same hardware resources. Furthermore, hardware resources are assigned to threads implicitly as determined by the SMT instruction fetch (Ifetch) policy, without the control of the OS. Both factors cause a lack of control over how individual threads are executed, which can frustrate the work of the job scheduler. This presents a problem for general purpose systems, where the OS job scheduler cannot enforce priorities, and also for embedded systems, where it would be difficult to guarantee worst-case execution times. In this paper, we propose a novel strategy that enables a two-way interaction between the OS and the SMT processor and allows the OS to run jobs at a certain percentage of their maximum speed, regardless of the workload in which these jobs are executed. In contrast to previous approaches, our approach enables the OS to run time-critical jobs without dedicating all internal resources to them so that non-time-critical jobs can make significant progress as well and without significantly compromising overall throughput. In fact, our mechanism, in addition to fulfilling OS requirements, achieves 90 precent of the throughput of one of the best currently known fetch policies for SMTs.en_US
dc.languageengen_US
dc.relation.ispartofIEEE Transactions on Computersen_US
dc.sourceIEEE Transactions On Computers [ISSN 0018-9340], v. 55 (7), p. 785-799, (Julio 2006)en_US
dc.subject1203 Ciencia de los ordenadoresen_US
dc.subject330406 Arquitectura de ordenadoresen_US
dc.subject120324 Teoría de la programaciónen_US
dc.subject.otherMultithreaded processorsen_US
dc.subject.otherSimultaneous multithreadingen_US
dc.subject.otherIlpen_US
dc.subject.otherThread-level parallelismen_US
dc.subject.otherPerformance predictabilityen_US
dc.subject.otherReal timeen_US
dc.subject.otherOperating systemsen_US
dc.titlePredictable performance in SMT processors: synergy between the OS and SMTsen_US
dc.typeinfo:eu-repo/semantics/Articleen_US
dc.typeArticleen_US
dc.identifier.doi10.1109/TC.2006.108en_US
dc.identifier.scopus33744824945-
dc.identifier.isi000237631000001-
dc.contributor.authorscopusid55129883300-
dc.contributor.authorscopusid6603587864-
dc.contributor.authorscopusid6701361478-
dc.contributor.authorscopusid36476145100-
dc.contributor.authorscopusid7401734996-
dc.contributor.authorscopusid24475914200-
dc.identifier.eissn1557-9956-
dc.description.lastpage799en_US
dc.identifier.issue7-
dc.description.firstpage785en_US
dc.relation.volume55en_US
dc.investigacionIngeniería y Arquitecturaen_US
dc.type2Artículoen_US
dc.contributor.daisngid268834-
dc.contributor.daisngid1769309-
dc.contributor.daisngid393539-
dc.contributor.daisngid30881890-
dc.contributor.daisngid440299-
dc.contributor.daisngid41870-
dc.description.numberofpages15en_US
dc.utils.revisionen_US
dc.contributor.wosstandardWOS:Cazorla, FJ-
dc.contributor.wosstandardWOS:Knijnenburg, PMW-
dc.contributor.wosstandardWOS:Sakellariou, R-
dc.contributor.wosstandardWOS:Fernandez, E-
dc.contributor.wosstandardWOS:Ramirez, A-
dc.contributor.wosstandardWOS:Valero, M-
dc.date.coverdateJulio 2006en_US
dc.identifier.ulpgces
dc.description.jcr1,426
dc.description.jcrqQ1
dc.description.scieSCIE
item.grantfulltextnone-
item.fulltextSin texto completo-
crisitem.author.deptDepartamento de Informática y Sistemas-
crisitem.author.fullNameFernández García, Enrique-
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