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Please use this identifier to cite or link to this item: http://hdl.handle.net/10553/72710
DC FieldValueLanguage
dc.contributor.authorCazorla, FJen_US
dc.contributor.authorKnijnenburg, PMWen_US
dc.contributor.authorSakellariou, Ren_US
dc.contributor.authorFernández, E.en_US
dc.contributor.authorRamirez, Aen_US
dc.contributor.authorValero, Men_US
dc.date.accessioned2020-05-21T14:28:49Z-
dc.date.available2020-05-21T14:28:49Z-
dc.date.issued2004en_US
dc.identifier.isbn978-3-540-22924-7en_US
dc.identifier.issn0302-9743en_US
dc.identifier.otherWoS-
dc.identifier.urihttp://hdl.handle.net/10553/72710-
dc.description.abstractSince embedded systems require ever more compute power, SMT processors are viable candidates for future high performance embedded processors. However, SMTs exhibit unpredictable performance due to uncontrolled interaction of threads. Hence, the SMT hardware needs to be adapted in order to meet (soft) real time constraints. We show by a simple policy that the OS can exercise control over the execution of a thread which is required for real time constraints.en_US
dc.languageengen_US
dc.publisherSpringeren_US
dc.relation.ispartofLecture Notes in Computer Scienceen_US
dc.sourceDanelutto M., Vanneschi M., Laforenza D. (eds) / Euro-Par 2004 Parallel Processing. Lecture Notes in Computer Science, [ISSN 0302-9743], vol 3149, p. 535-540, (2004). Springer, Berlin, Heidelberg. (2004)en_US
dc.subject3304 Tecnología de los ordenadoresen_US
dc.subject330412 Dispositivos de controlen_US
dc.titleFeasibility of QoS for SMTen_US
dc.typeinfo:eu-repo/semantics/conferenceObjecten_US
dc.typeConferenceObjecten_US
dc.relation.conference10th International Euro-Par Conference on Parallel Processingen_US
dc.identifier.doi10.1007/978-3-540-27866-5_70en_US
dc.identifier.scopus35048828987-
dc.identifier.isi000223792500070-
dc.contributor.authorscopusid55129883300-
dc.contributor.authorscopusid6603587864-
dc.contributor.authorscopusid6701361478-
dc.contributor.authorscopusid36476145100-
dc.contributor.authorscopusid7401734996-
dc.contributor.authorscopusid24475914200-
dc.identifier.eissn1611-3349-
dc.description.lastpage540en_US
dc.description.firstpage535en_US
dc.relation.volume3149en_US
dc.investigacionIngeniería y Arquitecturaen_US
dc.type2Actas de congresosen_US
dc.contributor.daisngid268834-
dc.contributor.daisngid1769309-
dc.contributor.daisngid393539-
dc.contributor.daisngid6404672-
dc.contributor.daisngid5085653-
dc.contributor.daisngid41870-
dc.description.numberofpages6en_US
dc.identifier.eisbn978-3-540-27866-5-
dc.utils.revisionSíen_US
dc.contributor.wosstandardWOS:Cazorla, FJ-
dc.contributor.wosstandardWOS:Knijnenburg, PMW-
dc.contributor.wosstandardWOS:Sakellariou, R-
dc.contributor.wosstandardWOS:Fernandez, E-
dc.contributor.wosstandardWOS:Ramirez, A-
dc.contributor.wosstandardWOS:Valero, M-
dc.date.coverdateDiciembre 2004en_US
dc.identifier.ulpgcSíes
dc.description.jcr0,513
dc.description.jcrqQ4
item.grantfulltextnone-
item.fulltextSin texto completo-
crisitem.author.deptDepartamento de Informática y Sistemas-
crisitem.author.fullNameFernández García, Enrique-
crisitem.event.eventsstartdate31-08-2004-
crisitem.event.eventsenddate03-09-2004-
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