|Title:||Optimising long-latency-load-aware fetch policies for SMT processors||Authors:||Cazorla, Francisco J.
|UNESCO Clasification:||3304 Tecnología de los ordenadores
330412 Dispositivos de control
Load miss predictors
Long latency loads
SMT processors, et al
|Issue Date:||2004||Journal:||International Journal of High Performance Computing and Networking||Abstract:||Simultaneous multithreading (SMT) processors fetch instructions from several threads, increasing the available instruction level parallelism of each thread exposed to the processor. In an SMT the fetch engine decides which threads enter the processor and have priority in using resources. Hence, the fetch engine determines how shared resources are allocated, playing a key role in the final performance of the machine. When a thread experiences an L2 cache miss, critical resources can be monopolised for a long time, throttling the execution of remaining threads. Several approaches have been proposed to cope with this problem. The first contribution of this paper is the evaluation and comparison of the three best published policies addressing the long latency load problem. The second and main contributions of this paper are that we have proposed improved versions of these three policies. Our results show that the improved versions significantly enhance the original ones in both throughput and fairness.||URI:||http://hdl.handle.net/10553/72705||ISSN:||1740-0562||DOI:||10.1504/IJHPCN.2004.009267||Source:||International Journal of High Performance Computing and Networking [ISSN 1740-0562], v. 2 (1), p. 45-54, (Enero 2004)|
|Appears in Collections:||Artículos|
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