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Title: SHyLoC 2.0: a versatile hardware solution for on-board data and hyperspectral image compression on future space missions
Authors: Barrios Alfaro, Yubal 
Sánchez Clemente, Antonio José 
Santos, Lucana 
Sarmiento, Roberto 
UNESCO Clasification: 3325 Tecnología de las telecomunicaciones
Keywords: Compression Algorithms
Field Programmable Gate Arrays
Hardware Implementations
Hyperspectral Imaging
On-Board Data Processing, et al
Issue Date: 2020
Journal: IEEE Access 
Abstract: In this paper, we present the design, implementation and results of a set of IP cores that perform on-board hyperspectral image compression according to the CCSDS 123.0-B-1 lossless standard, specifically designed to be suited for on-board systems and for any kind of hyperspectral sensor. As entropy coder, the sample-adaptive entropy coder defined in the 123.0-B-1 standard or the low-complexity block-adaptive encoder defined by the CCSDS 121.0-B-2 lossless standard could be used. Both IPs, 123.0-B-1 and 121.0-B-2, are part of SHyLoC 2.0, and can be used together for compression of hyperspectral images, being also possible the compression of any kind of data using only the 121-IP. SHyLoC 2.0 improves and extends the capabilities of SHyLoC 1.0, currently available at the ESA IP Cores library, increasing its compression efficiency and throughput, without compromising the resources footprint. Moreover, it incorporates new features, such as the unit-delay predictor option defined by the CCSDS 121.0-B-2 standard, and burst capabilities in the external memory interface of the CCSDS 123-IP, among others. Dedicated architectures have been designed for all the possible input image sample arrangements, in order to maximise throughput and reduce the hardware resources utilization. The design is technology-agnostic, enabling the mapping of the VHDL code in different FPGAs or ASICs. Results are presented for a representative group of well-known space-qualified FPGAs, including the new NanoXplore BRAVE family. A maximum throughput of 150 MSamples/s is obtained for Xilinx Virtex XQR5VFX130 when the SHyLoC 2.0 CCSDS-123 IP is configured in Band-Interleaved by Pixel (BIP) order, using only the 4% of LUTs and less than the 1% of internal memory.
ISSN: 2169-3536
DOI: 10.1109/ACCESS.2020.2980767
Source: IEEE Access [ISSN 2169-3536],v. 8, p. 54269-54287
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