|Title:||Versatile CMOS current conveyor for digital VLSI systems with low-voltage power supply||Authors:||García, José C.
Montiel-Nelson, Juan A.
|UNESCO Clasification:||3307 Tecnología electrónica||Keywords:||Cmos Design
High Dynamic Range, et al
|Issue Date:||2019||Journal:||Journal of Low Power Electronics||Abstract:||A low voltage supply CMOS current conveyor circuit for digital input signals from 0.25 V up to 1.2 V is presented. The circuit is optimized and pre-layout simulated in a 65 nm CMOS process technology. At the target design voltage of 1.2 V, the current conveyor has a propagation delay of 2.86 ns, an energy consumption of only 80.9 pJ, and energy-delay product (EDP) of 231 pJns for resistive load of 10 kΩ. Superior performance of this work is demonstrated through comparison with other similar published work at a frequency of 5 MHz. It is shown that the proposed circuit is suitable for digital signaling. The developed CMOS circuit perfoms correctly until 50 MHz and its EDP is 31 pJns at 10 kΩ||URI:||http://hdl.handle.net/10553/70152||ISSN:||1546-1998||DOI:||10.1166/jolpe.2019.1617||Source:||Journal of Low Power Electronics [ISSN 1546-1998], v. 15 (3), p. 323-328|
|Appears in Collections:||Artículos|
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