Approximate TMR for selective error mitigation in FPGAs based on testability analysis

Abstract

The use of approximate logic circuits in error mitigation techniques has appeared in the recent years as a way of achieving a sufficient fault coverage at a reduced cost, substituting the exact replicas of the target circuit with simplified versions of it. This approach, when applied to the well-known TMR scheme, results in the Approximate TMR (ATMR) technique, where the target circuit is voted along with two approximate circuits for selective error masking. Such approximate circuits should ideally present an optimal trade-off between costs and error mitigation capabilities, which can be achieved through different approximation generation approaches. This idea be-comes specially promising in FPGA applications because of the flexibility that such devices offer. Depending on the availability of resources and the reliability requirements, the most convenient ATMR configuration can be chosen. However, the particularities of the FPGA architecture must be taken into account in order to generate efficient approximations. This paper reviews some concepts of the ATMR and gives some ideas on its application to FPGA designs. In particular, the use of testability measures to conduct the generation of approximate logic circuits is proposed in this work. The proposed approach has a wide scalability and has been validated by using fault injection, showing that ATMR-hardened designs in FPGAs can be intrinsically more robust than full TMR.